DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/13/2025. Claims 1-18 are pending in the Application, of which Claims 1 and 10 are independent.
Continuity Priority information
The present Application 19053083 filed 02/13/2025 claims foreign priority to INDIA, Application No. 02421012230, filed 02/21/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/13/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 10, the limitation “data comprises a potential control code” is indefinite, because the specification fails to sufficiently define “a potential control code”.
The limitation “lock a seed used to descramble the remaining incoming data” is indefinite, because the specification fails to sufficiently define the term “lock a seed”.
Any Claims not specifically mentioned above are rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dubrova et al. (PgPub. US 20160349314) Pub. Date: 2016-12-01.
Regarding independent Claims 1 and 10, Dubrova discloses remote test management devices for remotely testing the digital logical circuit in the electronic devices, comprising:
one or more channels to receive data from a device under test (DUT) through a test fixture; [0064] With reference to FIGS. 4 to 6, electronic device 320 comprises a digital logic circuit 101, the CUT, which implements at least part of the functionality which electronic device 320 provides, and a test module 322 for performing logic tests on CUT 101. Electronic device 320 may, e.g., be an IC 1100 illustrated in FIG. 11, comprising a digital logic circuit 1101 and a test module 1102, such as a microprocessor, an ASIC, or an FPGA.
data being transmitted by the DUT [0051] The response of CUT 101 to the input values defined by the test patterns is made available at test outputs 112 corresponding to “channels” of the combinational logic. Finally, scan mode of CUT 101 is selected again, and one clock cycle is applied to unload the output values of scan chains 114 through test outputs 112.
one or more processors configured to execute code; [0060] Further with reference to FIG. 3, remote test management device 310 comprises processing means, such as a processing unit 311 and a memory 312 comprising a computer program 313.
acquire a state of a linear feedback shift register (LFSR); extract a known portion of the LFSR as an LFSR value; shift the LFSR value to a predetermined number of times to produce a new value of the LFSR; [0049] FIG. 2, LBIST module 102, comprises a PRPG 201, which may be based on a Linear Feedback Shift Register (LFSR), for generating pseudo-random test patterns. [0068] An alternative embodiment 600 of test module 322 is now described with reference to FIG. 6. Similar to test module 500, test module 600 comprises a PRPG 201 for generating pseudo-random test patterns and an MISR 203 for compacting test responses received from CUT 101 via test outputs 112 into a test signature.
compare the new value of the LFSR to the value of incoming data received through the channel to determine if the value of the incoming data comprises a potential control code; [0069] Test module 600 further comprises a decision logic 604 configured to compare the test signature obtained from MISR 203 to an expected signature, as is known in the art. However, different from LBIST module 102, the expected signature is not stored or hard-wired in test module 600 but received from the remote management device, via communication module 607.
repeat the shift of the LFSR value and the compare of the new value of the LFSR to acquire a predetermined number of potential control codes; and compare the predetermined number of potential control codes to known control code values to determine if the potential control codes are valid. To this end, communication module 607 is configured to receive the expected signature and provide the received expected signature to decision logic 604, e.g., via a module 605 configured to temporarily store the expected signature. Decision logic 604 may further be configured to provide the result of the comparison, i.e., a test result, to communication module 607 which may further be configured to transmit information pertaining to the test result to the remote management device. Further optionally, decision logic 604 may be configured to make available the test result to an external circuit, e.g., a fault supervision unit provided together with electronic device 320, by means of a signal 115.
Regarding Claims 2-4, 11-13 Dubrova discloses, processors to shift the LFSR value one or more times; [0051] A test cycle typically involves selecting scan mode and serially loading a test pattern into scan chains 114 via test inputs 111. When scan chains 114 are fully loaded, normal mode of operation of CUT 101 is selected, via control signals 113, and one clock cycle is applied, thereby applying the loaded test pattern to the inputs of the combinational logic implemented by CUT 101. The response of CUT 101 to the input values defined by the test patterns is made available at test outputs 112 of the combinational logic. Finally, scan mode of CUT 101 is selected again, and one cock cycle is applied to unload the output values of scan chains 114 through test outputs 112. While the outputs are shifted out of scan chains 114, the next test pattern can be loaded into scan chains 114.
Regarding Claims 5, 6, 8, 14, 15, 17, Dubrova discloses the code that causes the one or more processors to compare the new value of the LFSR to the value of incoming data. [0076] In FIG. 8, receiving 806 an expected signature corresponding to the test patterns from the remote test management device, and determining 807 a test result based on a comparison of the expected signature received with the test signature. Optionally, method 800 may further comprise transmitting 808 information pertaining to the test result to the remote test management device.
Regarding Claims 7, 16, Dubrova discloses reinitializing the LFSR when the control codes are valid. [0049] LBIST module 102, in FIG. 2, comprises a PRPG 201, which may be based on a Linear Feedback Shift Register (LFSR), for generating pseudo-random test patterns which during testing are applied to CUT 101 via test inputs 111. The test patterns are generated based on one or more test parameters which are stored 202 or hard-wired 202 in LBIST module 102. Typically, the test parameters comprise an initialization value, defining an initial state of PRPG 201, and a number of test patterns to be generated.
Regarding Claims 9,18, Dubrova discloses the DUT comprises receiving the data without receiving sideband signals. [0075] In FIG. 7, method 700 is performed by the electronic device and comprises receiving 701 one or more test parameters from a remote test management device, such as remote test management device 310, and generating 702 one or more test patterns based on the received test parameters.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: July 21, 2026
Non-Final Rejection 20260720
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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