Prosecution Insights
Last updated: July 17, 2026
Application No. 19/053,479

VERTICALLY STACKED LIGHT SENSORS

Non-Final OA §102
Filed
Feb 14, 2025
Priority
Apr 26, 2023 — provisional 63/498,309 +1 more
Examiner
KO, TONY
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
12m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
780 granted / 888 resolved
+27.8% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
20 currently pending
Career history
903
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
43.0%
+3.0% vs TC avg
§102
43.8%
+3.8% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 888 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a first photodetector comprising a doped collector region in a first substrate; a gate structure arranged on a first surface of the first substrate and proximate to the doped collector region” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 10, 11, 13 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hseih et al (US 20190096932). Regarding claim 1, Hseih et al teach (Figs. 1-15) An integrated chip, comprising: a first photodetector (362a) arranged in a first substrate (356), wherein the first photodetector absorbs light in a first wavelength range; a second substrate (340) under the first substrate; a second photodetector arranged (314b) on the second substrate, wherein the second photodetector absorbs light in a second wavelength range different from the first wavelength range ([0080-0081]); and a dielectric structure (light pipe [0128 and 0129 and 0060]) between a first surface of the first substrate and a first surface of the second substrate. Regarding claim 2, Hseih et al teach (Fig. 10) the dielectric structure ([0128]) comprises a light guide region vertically extending between the first photodetector and the second photodetector. Regarding claims 10 and 17, Hseih et al teach (Figs. 1-10) An integrated chip and method of manufacturing, comprising: a first photodetector (362a) comprising a doped collector region (MOSFET) in a first substrate; a gate structure (gate of MOSFET – also element 366) arranged on a first surface of the first substrate and proximate to the doped collector region; a second photodetector (314) arranged on a second substrate; and a stack of layers (318 and 319) between the first substrate and the second substrate, wherein an optical path region is arranged in the stack of layers and is laterally aligned with the first and second photodetectors (see figure 3). Regarding claim 11, Hseih et al teach the optical path region is configured to direct incident light from the first photodetector to the second photodetector. Regarding claim 13, Hseih et al teach a height of the optical path region (length of 318 and 319) is greater than a height of the gate structure (part of dotted circle area of EPI-layer shown in figure 3). Allowable Subject Matter Claims 3-8, 12, 14-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY KO whose telephone number is (571)272-1926. The examiner can normally be reached Monday-Friday 9-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached at 571-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY KO/Primary Examiner, Art Unit 2878 TK
Read full office action

Prosecution Timeline

Feb 14, 2025
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12680868
COMPARATOR, LIGHT DETECTION ELEMENT, AND ELECTRONIC DEVICE
2y 0m to grant Granted Jul 14, 2026
Patent 12677487
IMAGING ELEMENT AND SEMICONDUCTOR ELEMENT
2y 2m to grant Granted Jul 07, 2026
Patent 12674704
SIGNAL GENERATION CIRCUIT AND LIGHT DETECTING UNIT
1y 11m to grant Granted Jul 07, 2026
Patent 12663297
OPTICAL SENSING ASSEMBLY AND ENCODER
2y 2m to grant Granted Jun 23, 2026
Patent 12659438
OPTICAL LOCALIZATION SYSTEM
2y 2m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
90%
With Interview (+2.4%)
2y 5m (~12m remaining)
Median Time to Grant
Low
PTA Risk
Based on 888 resolved cases by this examiner. Grant probability derived from career allowance rate.

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