DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3 and 5-17 are pending in this office action and presented for examination. Claims 1-3, 5-6, 9-13, and 16-17 are newly amended, and claim 4 is newly cancelled, by the response received July 30, 2026.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
On page 11, line 12, of the clean copy of the specification received July 30, 2026, “a N-bit” should be “an N-bit”. (As a comparison, see, for example, page 11, line 11, and page 11, line 14.)
Claim Objections
Claims 1-3, 5-15, and 17 are objected to because of the following informalities. Appropriate correction is required.
Claim 1, lines 10-18, recites within “hardware control circuitry configured to… to populate … to flush”; the second and third instances of “to” in the language above appear to be duplicative.
Claims 2-3 and 5-15 are objected to for failing to alleviate the objection of claim 1 above.
Claim 17, lines 11-19, recites within “hardware control circuitry configured to… to populate … to flush”; the second and third instances of “to” in the language above appear to be duplicative.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 5-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “a subsequent prediction identifying a change in the predicted outcome of the second branch instruction” in lines 15-16. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., page 8, lines 28-29) does not appear to provide support for the subsequent prediction itself identifying a change in the predicted outcome of the second branch instruction. Note that claim 2 recites the similar limitation “the subsequent prediction identifies that the predicted outcome of the second branch instruction has changed from taken to not-taken” in lines 6-7. Note that claim 11 recites the similar limitation “the subsequent prediction identifies that the predicted outcome of the second branch instruction has changed from taken to not-taken” in lines 3-4. Note that claim 12 recites the similar limitation “the subsequent prediction identifying a change in a predicted outcome of the first branch instruction” in lines 4-6. Note that claim 13 recites the similar limitation “the subsequent prediction identifying the change in the predicted outcome of the first branch instruction” in lines 2-3.
Claims 2-3 and 5-15 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 16 recites the limitation “identifying, in a subsequent prediction, a change in the predicted outcome of the second branch instruction” in lines 16-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., page 8, lines 28-29) does not appear to provide support for identifying, in a subsequent prediction itself, a change in the predicted outcome of the second branch instruction.
Claim 17 recites the limitation “a subsequent prediction identifying a change in the predicted outcome of the second branch instruction” in lines 16-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., page 8, lines 28-29) does not appear to provide support for the subsequent prediction itself identifying a change in the predicted outcome of the second branch instruction.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 5-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue” in lines 16-18. However, it is indefinite as to whether the “in the hardware fetch queue” language is merely applying to “instruction addresses up to and including the second branch instruction address” in claim 1, lines 17-18, or is also applying to “instruction addresses subsequent to a second branch instruction address of the second branch instruction” of claim 1, lines 16-17, as well. In addition, it is indefinite as to whether “instruction addresses subsequent to a second branch instruction address” refers to instruction addresses that follow a second branch instruction address in memory (i.e., fall-through instruction addresses), or instruction addresses that follow a second branch instruction in a flow of execution (which may include a target instruction address). Similarly, see “instructions of the second instruction block subsequent to the second branch instruction” in claim 2, lines 4-5; “a sequentially next instruction block subsequent to the second instruction block” in claim 11, lines 5-6; “instruction addresses from the first instruction block subsequent to the first branch instruction” in claim 12, lines 2-3; “instruction addresses subsequent to the first branch instruction” in claim 12, line 7; and “a sequentially next instruction block subsequent to the first instruction block” in claim 13, lines 3-4. In particular, note that claim 12 appears to recite “instruction addresses from the first instruction block subsequent to the first branch instruction”, in lines 2-3, as instruction addresses which might be used in the alternative, and “instruction addresses subsequent to the first branch instruction” in line 7 as instruction addresses which might be flushed, but both sets of instruction addresses are being characterized as subsequent to the first branch instruction.
Claims 2-3 and 5-15 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 3 recites the limitation “the subsequent identification” in line 2. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 12 recites the limitation “buffer circuitry to store, as alternative instruction addresses, instruction addresses from the first instruction block subsequent to the first branch instruction” in lines 1-3. Claim 12 further recites the limitation “to identify the alternative instruction addresses in the fetch queue” in line 9. Therefore, it is indefinite as to whether the alternative instruction addresses are in the buffer circuitry or the fetch queue.
Claim 12 recites the limitation “a predicted outcome of the first branch instruction “ in lines 5-6. However, it is indefinite as to whether this limitation is the same as, or different from, a predicted outcome of the first branch instruction of the limitation “a predicted outcome of both of the first branch instruction and the second branch instruction” as recited in claim 1, lines 11-12 (to the extent to that the aforementioned limitation of claim 1, lines 11-12, is to be interpreted as “a predicted outcome of the first branch instruction and a predicted outcome of the second branch instruction”, i.e., two separate predicted outcomes rather than one combined collective predicted outcome).
Claim 13 is rejected for failing to alleviate the rejections of claim 12 above.
Claim 16 recites the limitation “flushing instruction addresses subsequent to a second branch instruction address of the second branch instruction and retaining instruction addresses up to and including the second branch instruction address in the hardware fetch queue” in lines 17-19. However, it is indefinite as to whether the “in the hardware fetch queue” language is merely applying to “instruction addresses up to and including the second branch instruction address” in claim 16, lines 18-19, or is also applying to “instruction addresses subsequent to a second branch instruction address of the second branch instruction” of claim 16, lines 17-18, as well. In addition, it is indefinite as to whether “instruction addresses subsequent to a second branch instruction address” refers to instruction addresses that follow a second branch instruction address in memory (i.e., fall-through instruction addresses), or instruction addresses that follow a second branch instruction in a flow of execution (which may include a target instruction address).
Claim 17 recites the limitation “flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue” in lines 17-19. However, it is indefinite as to whether the “in the hardware fetch queue” language is merely applying to “instruction addresses up to and including the second branch instruction address” in claim 17, lines 18-19, or is also applying to “instruction addresses subsequent to a second branch instruction address of the second branch instruction” of claim 17, lines 17-18, as well. In addition, it is indefinite as to whether “instruction addresses subsequent to a second branch instruction address” refers to instruction addresses that follow a second branch instruction address in memory (i.e., fall-through instruction addresses), or instruction addresses that follow a second branch instruction in a flow of execution (which may include a target instruction address)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 9, 12-13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emma et al. (Emma) (US 5434985) in view of Ishii et al. (Ishii ‘811) (US 20200310811 A1) in view of Shah et al. (Shah) (US 20120290821 A1) in view of Lee et al. (Lee) (US 20220357953 A1).
Consider claim 1, Emma discloses an apparatus comprising: hardware prediction entry storage circuitry configured to store a plurality of prediction entries (col. 12, line 40-42, multibranch history table 401, denoted MBHT. Each entry in the MBHT 401) comprising a multi-taken entry (col. 12, lines 48-55, each branch is characterized by two addresses, e.g., BG1 comprises the pair of addresses BA1 and TA1. The first address is the address of the branch instruction, [BA1]. The second address is the address of the corresponding target instruction, TA1. The compound entry <BG1,BG2> contains four addresses, and is stored in a location in the table that is determined by the first address of its corresponding triple), the multi-taken entry identifying: a first branch instruction (col. 12, line 63, BA1=A+na-1) comprised in a first instruction block (col. 12, lines 45-46, first branch group, denoted BG1; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 54-58, for example, there is a branch group that begins at symbolic address A and contains n.sub.a instructions. The last instruction in the branch group is a taken branch that goes to a new branch group that begins at symbolic address B) and configured to divert control flow to a first target address (col. 12, line 63, TA1=B; col. 11, lines 56-58, a taken branch that goes to a new branch group that begins at symbolic address B) identifying a second instruction block (col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X); and a second branch instruction (col. 12, line 64, BA2=B+b; col. 11, lines 59-60, at an offset of b instructions from address B, there is a conditional branch) comprised in the second instruction block (col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X) and configured to divert control flow to a second target address (col. 12, line 64, TA2=C; col. 11, lines 60-61, a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction); and hardware control circuitry configured to, in response to a prediction associated with the multi-taken entry, the prediction identifying a predicted outcome of both of the first branch instruction and the second branch instruction in which the first branch instruction is predicted to be taken, to fetch based on the prediction (col. 10, lines 31-34, the Multibranch prediction device 201 predicts the multiple branches per cycle that connect the branch groups. The Multibranch prediction device 201 also initiates the fetches of these branch groups; col. 12, line 65, to col. 13, line 4, referring to FIG. 3, if the MBHT 401 were subsequently searched using address A, this entry would be found. This search can be implemented using combinational logic to compare the address held in PFAR 402 to the address fields of entries in MBHT 401. The entry indicates that there is a taken branch at address A+na-1 that goes to address B, and another taken branch at address B+b that goes to address C; col. 11, lines 39-47, to summarize, FIG. 2 illustrates the general case in which n branch groups are predicted per cycle. One preferred embodiment details the operation of multibranch prediction device for n=2, i.e., a specific embodiment for a multibranch prediction device that predicts two branches per cycle. The point n=2 is chosen as the simplest case that demonstrates the invention, but it is understood by those skilled in the art that this is not a limitation).
However, Emma does not disclose a hardware fetch queue configured to identify a sequence of instructions to be fetched for execution; the aforementioned hardware control circuitry configured to populate the hardware fetch queue based on the aforementioned prediction; and, in response to a subsequent prediction identifying a change in the predicted outcome of the second branch instruction, to flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue.
On the other hand, Ishii ‘811 discloses a hardware fetch queue configured to identify a sequence of instructions to be fetched for execution ([0002], lines 2-4, a fetch queue may be provided to identify instructions to be fetched from memory for execution by the execution circuitry); control circuitry to populate the fetch queue based on a prediction ([0003], lines 3-19, in particular, execution of such an instruction flow changing instruction may cause a discontiguous change in the address, such that the next instruction executed after the instruction flow changing instruction is at a target address determined for the instruction flow changing instruction, rather than the immediately following instruction within the instruction address space. In order to seek to ensure that the fetch queue identifies the instructions that actually require execution by the execution circuitry, it is known to provide prediction circuitry to make predictions in respect of such instruction flow changing instructions, for example to identify whether those instructions will be taken or not taken, and, if those instructions are taken, to predict the target address of the next instruction to be executed. The predictions made by the prediction circuitry can then be used to control which instructions are identified in the fetch queue).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ishii ‘811 with the invention of Emma in order to increase system performance, as decoupling, via a queue, the determination of instruction addresses to fetch with the actual fetching of instructions at a memory enables the former functionality to continue even when the latter functionality is stalled.
However, the combination thus far does not entail the aforementioned hardware control circuitry configured to, in response to a subsequent prediction identifying a change in a predicted outcome of the second branch instruction, to flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue.
On the other hand, Shah discloses hardware control circuitry configured to, in response to a subsequent ([0101], lines 1-5, in one embodiment, a BTC hit causes instructions at target address 456 to be fetched by the IFU. This prediction by the BTC might not be accurate in all instances. In one embodiment, every fetch initiated by the IFU also causes a lookup in the more accurate, but slower, DBP 460) prediction identifying a change in a predicted outcome of a branch instruction ([0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU), to flush instructions subsequent to a branch instruction address of the branch instruction and to retain instructions up to and including the branch instruction address ([0111], lines 1-11, the first row of table 600 covers the situation in which there is a hit in the BTC for a particular CTI and the DBP subsequently predicts that the particular CTI is not taken. In this implementation, the BTC entry is invalidated such that a subsequent occurrence of the CTI will not cause a hit. In this embodiment, the used bit may also be cleared since it is no longer a valid entry. Further, instructions that may have been fetched based on the BTC hit may need to be discarded since the CTI is no longer predicted to be taken; [0080], lines 7-10, for instructions that are not flushed or otherwise cancelled due to mispredictions or exceptions, instruction processing may end when instruction results have been committed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shah with the combination of Emma and Ishii ‘811 in order to increase prediction accuracy (Shah, [0101], lines 12-15). Note that Shah’s teaching of flushing a branch path that is mispredicted, when applied to the combination of Emma and Ishii which entails a branch path that includes both instructions and instruction addresses in a fetch queue, and a “second” branch instruction which is predicted, results in the overall claim limitation of hardware control circuitry configured to, in response to a subsequent prediction identifying a change in the predicted outcome of the second branch instruction, to flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue. Additionally, flushing mispredicted instruction addresses in a fetch queue maintains program correctness.
For the purposes of compact prosecution, to any extent to which the aforementioned combination as explained above might be argued to not entail the hardware control circuitry configure to, in response to a subsequent prediction identifying a change in the predicted outcome of the second branch instruction, to flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in the hardware fetch queue (which Examiner would not agree with), Lee nevertheless explicitly discloses hardware control circuitry configured to, in response to a subsequent prediction identifying a change in a predicted outcome of a second branch instruction, to flush instruction addresses subsequent to a second branch instruction address of the second branch instruction and to retain instruction addresses up to and including the second branch instruction address in a hardware fetch queue ([0046], lines 8-14, it is not necessary for the entire fetch queue 68 to be flushed. In particular, for a particular instruction for which a correction has been made, there is no need for instructions prior to that instruction in the fetch queue 68 to be flushed. This is because a change to the prediction of the particular instruction has no effect on whether or not earlier instructions are executed; also generally see [0044], lines 10-17, in the event that the contents of the fetch queue 68 are considered to be incorrect (for instance if the contents of the fetch queue are considered to have been fetched sequentially where the prediction information suggests that a branch should have been taken), the contents of the fetch queue can be flushed and replaced with addresses to instructions along a revised control flow path), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the aforementioned teaching of Lee with the combination of Emma, Ishii ‘811, and Shah in order to maintain program correctness via preventing instructions on a mispredicted path from being fetched and executed, while allowing instructions on a non-mispredicted path to be fetched and executed.
Consider claim 2, the overall combination entails the apparatus of claim 1 (see above), wherein the hardware control circuitry is configured: to perform a decomposition of the second instruction block to generate an instruction sub-block comprising instructions of the second instruction block subsequent to the second branch instruction; and when the subsequent prediction identifies that the predicted outcome of the second branch instruction has changed from taken to not-taken, to trigger a new prediction based on the instruction sub-block (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X).
Consider claim 3, the overall combination entails the apparatus of claim 1 (see above), wherein the hardware control circuitry is configured, when the subsequent identification identifies that the predicted outcome of the second branch instruction has changed from not-taken to taken, to trigger a new prediction based on a block of instructions identified by the second target address (Shah, [0102], lines 3-5, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430; [0113], lines 1-4, the situation in which the BTC predicts that a control transfer is not taken for a particular instruction, but the DBP predicts that the control transfer is taken (to an address Y); Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X).
Consider claim 5, the overall combination entails the apparatus of claim 1 (see above), wherein the subsequent prediction is performed using a higher accuracy predictor than the prediction (Shah, [0101], lines 1-5, in one embodiment, a BTC hit causes instructions at target address 456 to be fetched by the IFU. This prediction by the BTC might not be accurate in all instances. In one embodiment, every fetch initiated by the IFU also causes a lookup in the more accurate, but slower, DBP 460).
Consider claim 6, the overall combination entails the apparatus of claim 1 (see above), comprising further prediction circuitry configured to provide the subsequent prediction based on a global history of outcomes of branch instructions (Shah, [0087], lines 13-15, in one embodiment, the key provided from block 320 to predictor 340 is a hash of the address provided to instruction cache 312 with the global branch history).
Consider claim 9, the overall combination entails the apparatus of claim 1 (see above), comprising prediction circuitry responsive to receipt of an instruction block identifier to perform a lookup in the hardware prediction entry storage circuitry, wherein the prediction circuitry is responsive to a hit in the hardware prediction entry storage circuitry to generate the prediction (Emma, col. 10, lines 31-34, the Multibranch prediction device 201 predicts the multiple branches per cycle that connect the branch groups. The Multibranch prediction device 201 also initiates the fetches of these branch groups; col. 12, line 65, to col. 13, line 4, referring to FIG. 3, if the MBHT 401 were subsequently searched using address A, this entry would be found. This search can be implemented using combinational logic to compare the address held in PFAR 402 to the address fields of entries in MBHT 401. The entry indicates that there is a taken branch at address A+na-1 that goes to address B, and another taken branch at address B+b that goes to address C).
Consider claim 12, the overall combination entails the apparatus of claim 1 (see above), comprising buffer circuitry to store, as alternative instruction addresses, instruction addresses from the first instruction block subsequent to the first branch instruction (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X; Ishii ‘811, [0002], lines 2-4, a fetch queue may be provided to identify instructions to be fetched from memory for execution by the execution circuitry), wherein the hardware control circuitry is responsive to the subsequent prediction identifying a change in a predicted outcome of the first branch instruction (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X): to flush instruction addresses subsequent to the first branch instruction from the hardware fetch queue; and to identify the alternative instruction addresses in the hardware fetch queue (Shah, [0111], lines 1-11, the first row of table 600 covers the situation in which there is a hit in the BTC for a particular CTI and the DBP subsequently predicts that the particular CTI is not taken. In this implementation, the BTC entry is invalidated such that a subsequent occurrence of the CTI will not cause a hit. In this embodiment, the used bit may also be cleared since it is no longer a valid entry. Further, instructions that may have been fetched based on the BTC hit may need to be discarded since the CTI is no longer predicted to be taken; [0080], lines 7-10, for instructions that are not flushed or otherwise cancelled due to mispredictions or exceptions, instruction processing may end when instruction results have been committed).
Consider claim 13, the overall combination entails the apparatus of claim 12 (see above), wherein the hardware control circuitry is responsive to the subsequent prediction identifying the change in the predicted outcome of the first branch instruction (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X), to trigger a new prediction to be performed for a sequentially next instruction block subsequent to the first instruction block (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch; col. 11, lines 57-64, a new branch group that begins at symbolic address B. At an offset of b instructions from address B, there is a conditional branch that may be taken to address C, or it may fall through to a next sequential instruction. If the conditional branch falls through, there is an unconditional branch at an offset of n.sub.b-1 instructions from address B that is taken to address X; col. 24, lines 38-45, on Cycle #34, the seventh execution of the branch group at B occurs, and this time the successor is found to be X, not C as was the case in the first six executions. This represents an incorrect branch prediction, so it causes the pipeline to restart on Cycle #35. The restart of Cycle #35 is accomplished by staging address X for instruction fetching, clearing the remainder of the pipeline).
Independent claim 16 is directed to a method embodiment that is analogous to the apparatus embodiment of independent claim 1. All limitations of claim 16 are present in claim 1; therefore, claim 16 is rejected for the same reason as claim 1 above.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emma, Ishii ‘811, Shah, and Lee as applied to claim 6 above, and further in view of Jarvis et al. (Jarvis) (US 20230315475 A1).
Consider claim 7, the combination thus far entails the apparatus of claim 6 (see above), but does not entail the further prediction circuitry is tagged geometric history length (TAGE) prediction circuitry configured to predict whether conditional branch instructions will be taken or not based on a plurality of TAGE tables tagged by a range of lengths of execution history.
On the other hand, Jarvis discloses further prediction circuitry is tagged geometric history length (TAGE) prediction circuitry configured to predict whether conditional branch instructions will be taken or not based on a plurality of TAGE tables tagged by a range of lengths of execution history ([0001], lines 1-9, tagged geometric (TAGE) branch predictors use a combination of tagged TAGE table entries and increasing history lengths in order to generate predictions for a branch instruction. To do so, the TAGE branch predictor maintains a single, large global branch history describing whether previously encountered branches were taken or not taken. Portions of the global branch history of geometrically increasing lengths are used to index TAGE tables to generate the prediction; [0033], lines 1-11, to generate a prediction 202 for a given branch instruction, the TAGE branch predictor 200 calculates, for each TAGE table 204a-n, a tag 216a-n. Each tag 216a-n is calculated as a function (e.g., by hashing, XOR-ing, and the like) of the PC 210 and the bits of the global branch history 206 used by the corresponding TAGE table 204a-n. Though the indexes 208a-n and tags 216a-n are both generated as a function of the PC 210, the particular functions used to calculate the indexes 208a-n and tags 216a-n are different. For example, in some implementations, tags 216a-n and indexes 208a-n are of different lengths).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Jarvis with the combination of Emma, Ishii ‘811, Shah, and Lee, in order to obtain increased branch prediction accuracy.
Consider claim 8, the overall combination entails the apparatus of claim 7 (see above), wherein the execution history is a global execution history common to all branch instructions (Jarvis, [0001], lines 1-9, tagged geometric (TAGE) branch predictors use a combination of tagged TAGE table entries and increasing history lengths in order to generate predictions for a branch instruction. To do so, the TAGE branch predictor maintains a single, large global branch history describing whether previously encountered branches were taken or not taken. Portions of the global branch history of geometrically increasing lengths are used to index TAGE tables to generate the prediction; [0033], lines 1-11, to generate a prediction 202 for a given branch instruction, the TAGE branch predictor 200 calculates, for each TAGE table 204a-n, a tag 216a-n. Each tag 216a-n is calculated as a function (e.g., by hashing, XOR-ing, and the like) of the PC 210 and the bits of the global branch history 206 used by the corresponding TAGE table 204a-n. Though the indexes 208a-n and tags 216a-n are both generated as a function of the PC 210, the particular functions used to calculate the indexes 208a-n and tags 216a-n are different. For example, in some implementations, tags 216a-n and indexes 208a-n are of different lengths).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emma, Ishii ‘811, Shah, and Lee as applied to claim 2 above, and further in view of Ishii et al. (Ishii ‘812) (US 20200310812 A1).
Consider claim 10, the combination thus far entails the apparatus of claim 2 (see above), but does not entail that the hardware control circuitry is responsive to an identification that the second branch instruction is a final instruction of the second instruction block, to omit the decomposition.
On the other hand, Ishii ‘812 discloses hardware control circuitry is responsive to an identification that a branch instruction is a final instruction of an instruction block, to omit behavior associated with instructions of an instruction block following a branch instruction ([0036], lines 1-10, However, the above assumption will only apply if the function call instruction was not a final instruction address in the associated block of instruction addresses that was considered when making a prediction for the predict block including that function call instruction. Accordingly, in one example implementation, the detection circuitry is arranged to suppress triggering the override condition when the instruction address of the associated function call instruction is a final instruction address in the specified block of instruction addresses; [0072], lines 1-3, there are a number of ways in which the detection circuitry could assess whether the function call instruction was the last instruction in the block).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ishii ‘812 with the combination of Emma, Ishii ‘811, Shah, and Lee, in order to preclude power and performance costs generally associated with instructions of an instruction block following a branch instruction, in the scenario in which the branch instruction is the final instruction of the instruction block. Note that Ishi ‘812’s teaching of hardware control circuitry responsive to an identification that a branch instruction is a final instruction of an instruction block, to omit behavior associated with instructions of an instruction block following a branch instruction, when applied to the combination of Emma, Ishii ‘811, Shah, and Lee, which entails a “second” branch instruction and a “second” instruction block, wherein decomposition is associated with instructions of an instruction block following a branch instruction, results in the overall claimed limitation.
Consider claim 11, the overall combination entails the apparatus of claim 10 (see above), wherein the hardware control circuitry is responsive to the identification that the second branch instruction is the final instruction of the second instruction block (Ishi ‘812, [0072], lines 1-3, there are a number of ways in which the detection circuitry could assess whether the function call instruction was the last instruction in the block), when the subsequent prediction identifies that the predicted outcome of the second branch instruction has changed from taken to not-taken (Shah, [0102], lines 3-9, in one embodiment, the prediction information generated by DBP 460 controls or trumps the prediction information produced by BTC 430. Thus, if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU; Emma, col. 12, line 47, second branch group, denoted BG2; col. 9, lines 23-29, Branch Group A sequence of instructions whose addresses are sequential, i.e., it is a non-disjoint sequence. Each branch group begins with a branch-target instruction, and continues with all instructions that are sequential to and including the first taken branch), to trigger a new prediction to be performed for a sequentially next instruction block subsequent to the second instruction block (Emma, col. 14, line 5, branch-wrong-guess (BWG); col. 14, lines 4-6, From FIG. 2, when the processor 203 initiates a program or recovers from a branch-wrong-guess (BWG), it provides a restart address on its address bus 214; col. 24, lines 38-45, on Cycle #34, the seventh execution of the branch group at B occurs, and this time the successor is found to be X, not C as was the case in the first six executions. This represents an incorrect branch prediction, so it causes the pipeline to restart on Cycle #35. The restart of Cycle #35 is accomplished by staging address X for instruction fetching, clearing the remainder of the pipeline; Ishi ‘812, [0054], lines 15-23, in the event that it is predicted that the predict block does not contain any branch instructions that are predicted as taken, then instead the next predict block can be identified by the address immediately following the address of the last instruction in the current predict block, with that address being provided to the other input of the multiplexer 15 (as indicated by the feedback loop 17 in FIG. 1), and with the prediction logic 30 then controlling the multiplexer appropriately).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emma, Ishii ‘811, Shah, and Lee as applied to claim 1 above, and further in view of Sturcken (US 6734538 B1).
Consider claim 14, the combination thus far discloses a system comprising: the apparatus of claim 1 (see above), but does not disclose that the apparatus is implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.
On the other hand, Sturcken discloses a system comprising: an apparatus, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (col. 1, lines 20-45, for example).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sturcken with the combination of Emma, Ishii ‘811, Shah, and Lee in order to create packaging efficiencies (Sturcken, col. 1, line 23). Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Emma, Ishii ‘811, Shah, and Lee as cited above, and the teaching of Sturcken cited above) according to known methods (Examiner submits that chips, packages, system components, boards, and so forth, were known, as reflected by Sturcken) to yield predictable results (the combination of Emma, Ishii ‘811, Shah, and Lee, implemented in the manner cited in Sturcken), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 15, the overall combination entails a chip-containing product comprising
the system of claim 14, wherein the system is assembled on a further board with at least one other product component (Sturcken, col. 1, lines 20-45, for example).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emma, Ishii ‘811, Shah, Lee, and Bouzguarrou et al. (Bouzguarrou) (US 20230195468 A1).
Independent claim 17 is directed to a non-transitory computer-readable embodiment that is analogous to the apparatus embodiment of independent claim 1. All limitations of claim 17 are present in claim 1, except for the recited “non-transitory computer-readable medium storing computer-readable code for fabrication of” the apparatus. On the other hand, Bouzguarrou discloses non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus (see paragraph [0062]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouzguarrou with the combination of Emma, Ishii ‘811, Shah, and Lee (see the rejection of claim 1) in order to facilitate fabrication and enable simulation, functional and/or formal verification, and testing of the concepts (Bouzguarrou, [0063]).
Response to Arguments
Applicant on page 10 argues: “The Specification is objected to because of various informalities. A Substitute Specification (in marked and clean forms) is being concurrently submitted. The submitted specification includes corrections consistent with each of the items enumerated as a-s on pages 2-3 of the Office Action. The Substitute Specification additionally includes the corrections to page 23 of the Substitute Specification that were made in response to item t listed in the Objections to the Drawings on page 4 of the Office Action. Withdrawal of the objection is respectfully requested.”
In view of the aforementioned amendments, the corresponding previously presented objections to the specification and drawings are withdrawn, except for one lingering facet of a previously presented objection — see the specification section above.
Applicant on page 10 argues: “The title has been amended as shown above. Withdrawal of the objection is respectfully requested.”
In view of the aforementioned amendment, the previously presented objection to the title is withdrawn. Examiner thanks Applicant for facilitating the indexing, classifying, and searching of the application.
Applicant on page 10 argues: “As noted above, the objection listed as enumerated item t is addressed in the Substitute Specification. In corrected FIG.6 (swapped identifiers 402 and 403), FIG. 7A (deleted second lead line near 601), and FIGs. 7B and 7C (replaced 624 with 650) are corrected to address the objections u, V and X, respectively. FIG. 7A is also amended to address objection W. In view of the amendments to the drawings and the specification, withdrawal of these objections is respectfully requested.”
In view of the aforementioned amendments, the corresponding previously presented objections to the specification and drawings are withdrawn.
Applicant on page 10 argues: “Applicant has amended claim 16 to remove contingent limitations identified by the Examiner.”
Examiner thanks Applicant for facilitating compact prosecution.
Applicant on page 10 argues: ‘In response to enumerated paragraph 10 of the Official Action, claim 1 has been amended to further clarify that it is the prediction that identifies "an outcome of both of the first branch instruction and the second branch instruction in which the first branch instruction is predicted to be taken". The claim has been further amended to recite "configured to".’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 11 argues: “In response to enumerated paragraph 11 of the Office Action, claim 1 has been amended to define a predicted outcome and has been amended to incorporate the subject matter of claim 4. It is therefore clear from the amended wording that the change is a change in the predicted outcome.”
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 11 argues: ‘In response to enumerated paragraph 12 in the Office Action, Applicant respectfully submits that the breadth of claim 1 language, does not make that language indefinite. The Examiner questions whether "subsequent to" the second branch instruction address refers to addresses that sequentially follow that address in memory, or addresses that follow the second branch instruction in the flow of execution (which could include the target address). The claim itself resolves this: claim 1 separately recites a "target address" for the second branch instruction, distinct from the "subsequent to address" language used for flushing/retaining. Because claim terms are presumed to have distinct meanings, "subsequent to the second branch instruction address" cannot be read to encompass the separately-claimed target address, and must instead refer to sequential/memory order. This reading is confirmed by the specification, which describes a sub-block beginning "at the address of the sequentially next instruction subsequent to the second branch instruction" expressly equating "subsequent to" with sequential address order. The mere presence of embodiments in which some instructions subsequent to the second branch instruction are retained and some are flushed does not render the claim indefinite. For example, where instructions are retained or flushed as blocks of instructions, at least some of the instructions subsequent to the second branch instruction may be maintained (any that fall in a same block of instructions) and at least some instructions subsequent to the second branch instruction are flushed (those in a different block).’
Examiner first notes that the first rationale for indefiniteness (see the second sentence of the paragraph) does not appear to be addressed via the argument.
Applicant argues (as reproduced above) that ‘"subsequent to the second branch instruction address" cannot be read to encompass the separately-claimed target address, and must instead refer to sequential/memory order.’ However, the language of various other claims cited in the rejection appear to be at odds with this argument. For example, claim 1, in view of Applicant’s argument, would appear to convey that instruction addresses that follow the second branch instruction address in sequential/memory order are flushed; however, it would be unclear as to why these instruction addresses that follow the second branch instruction address in sequential/memory order are flushed in the context of claim 2 which entails a change in the predicted outcome of the second branch instruction from taken to not-taken (given that a not-taken prediction entails predicting that instructions following a branch in sequential/memory order are speculatively fetched).
Applicant across pages 11-12 argues: ‘Regarding claim 12, it is noted that claim 1 refers to populating the fetch queue based on the prediction (the original prediction, rather than the subsequent prediction). The buffer- storage clause of claim 12 expressly limits its addresses to those "from the first instruction block". That is, the fall-through addresses never fetched because the first branch was predicted taken, consistent with the specification's buffer circuitry "enabl[ing] a response to a misprediction of the first branch instruction without having to repredict" the first block. The flush clause, by contrast, carries no such qualifier and instead operates on the second-instruction- block addresses already populated into the fetch queue under claim 1's original prediction. These are two distinct, non-overlapping address sets (first-block fall-through addresses held in the buffer, versus second-block addresses already in the queue) distinguished by the claim's own "from the first instruction block" language, and the sequence recited (populate, then flush the invalidated second-block addresses, then insert the buffered first-block alternatives) is fully consistent.’
However, Examiner first notes that the flush clause does not appear to be recited to be directed to second-instruction-block addresses. In addition, if such were the case, then the “subsequent to” language in the flush clause would not appear to be subsequent in sequential/memory order, which would be at odds with Applicant’s argument in the immediately preceding paragraphs of Applicant’s remarks. When the “subsequent to” language in the flush clause is interpreted to be subsequent in sequential/memory order, the recited “alternative instruction addresses” and the recited “instruction addresses subsequent to the first branch instruction” do not appear to be distinct and non-overlapping.
Applicant on page 12 argues: “In response to enumerated paragraph 13 of the Office Action, claim 2 has been amended to replace the comma with a colon. It is unambiguous from the amended wording that it is the hardware control circuitry that does the performing.”
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: ‘In response to enumerated paragraph 14 of the Office Action, claims 1 and 9 have been amended to consistently refer to "hardware prediction entry storage circuitry".’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: ‘In response to enumerated paragraph 15 of the Office Action, claim 12 has been amended to refer to "the subsequent prediction identifying a change in a predicted outcome of the first branch instruction". The subsequent prediction is identified in claim 1. The features of claim 12 introduce that the subsequent prediction identifies "a change in a predicted outcome of the first branch instruction". It is submitted that these features have sufficient antecedent basis.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: ‘In response to enumerated paragraph 16 of the Office Action, Applicant respectfully submits that claim 12 clearly defines buffer circuitry that stores "as alternative instruction addresses, instruction addresses from the first instruction block subsequent to the first branch instruction". The claim further defines that these alternative instruction addresses are identified in the hardware fetch queue (for example, they may be copied from the buffer circuitry or otherwise identified) when a condition is met, i.e., in response to the subsequent prediction identifying a change in a predicted outcome of the first branch instruction.’
However, it is unclear as to how copying alternative instruction addresses from a buffer to a hardware fetch queue would be considered “identify[ing]” the alternative instruction addresses “in the hardware fetch queue”. Similarly, it is unclear as to what it would mean for alternative instruction addresses that have been copied from the buffer to the hardware fetch queue to be “identified” by the hardware control circuitry (e.g., control circuitry 406), with respect to how these copied alternative instruction addresses are being “identified”, and for what purpose. In other words, Examiner submit that while it can be envisioned by a person of ordinary skill in the art how, upon a change in a predicted outcome of the first branch instruction, particular corresponding alternative instruction addresses might be identified in the location at which they reside in order to be used for the new prediction, it is unclear as to what identification would entail for alternative instruction addresses that have already been copied to a fetch queue from buffer circuitry. Because “identification” (which is associated with the hardware fetch queue in the claim) appears to correspond to functionality associated with the location at which alternative instruction addresses are stored in case there is a change in predicted outcome (which appears to be the buffer circuitry in the claim), it is unclear as to whether the claim is directed to alternative instruction addresses as stored in the buffer circuitry or as stored in the hardware fetch queue.
Applicant on page 12 argues: “Regarding enumerated paragraphs 17-22 in the Office Action, Applicant respectfully submits that the objections stated therein are overcome based at least upon the remarks presented above in response to enumerated paragraphs 10-12 in the Office Action and corresponding amendments made to claims 16 and 17.”
Examiner’s responses to arguments above are analogously applicable to the arguments directed towards the aforementioned enumerated paragraphs.
Applicant on page 12 argues: ‘The term "configured to" is used to mean that an element of an apparatus has a configuration able to carry out the defined operation (see, page 34, lines 28 - 29). Claim 2 requires that the control circuitry is configured (is able to) perform a decomposition. The fact that the decomposition is sometimes omitted under a particular circumstance (claim 10) does not mean that the control circuitry is unable to perform the decomposition ever. Thus, for at least these reasons, there is no contradiction between claims 2 and 10.’
In view of the Applicant’s arguments, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘Applicant has amended the independent claims to recite a hardware fetch queue, hardware prediction entry storage circuitry, and hardware control circuitry. Accordingly, withdrawal of the rejection is respectfully requested.’
In view of the aforementioned amendment, the associated previously presented rejection under 35 USC 101 is withdrawn.
Applicant on page 13 argues: “As a threshold matter, Applicant respectfully submits that relying on a combination of four distinct prior art documents to reject the independent claims is clearly unreasonable. If an Examiner continually adds separate documents to stitch together individual claim limitations, it becomes virtually impossible for any claim to be considered non-obvious. Such a mosaic of references strongly suggests an impermissible reliance on hindsight reconstruction rather than a prima facie case of obviousness.”
However, reliance on a large number of references (to any extent to which four is considered large) in a rejection does not, without more, weigh against the obviousness of the claimed invention. See In re Gorman, 933 F.2d 982, 18 USPQ2d 1885 (Fed. Cir. 1991). Applicant does not elaborate on what number of references would not be clearly unreasonable. Examiner also notes that the fourth reference was provided for the purposes of compact prosecution to explicitly teach subject matter that Examiner nevertheless believed was rendered obvious by the prior art combination of the first three references.
Applicant on page 14 argues: “However, Shah explicitly teaches that the prediction conveyed to the Instruction Fetch Unit (IFU) is based on a selection from amongst these predictors. Specifically, Shah states in paragraph [0102] that "if BTC 430 predicted a branch to be taken and DBP 460 predicts that the branch not to be taken, unit 480 selects the DBP 460 outputs as branch prediction output information 482 and conveys it to the IFU". This architecture is further illustrated in Figure 4 of Shah, where the DBP prediction and the prediction from the BTC are both passed to the branch prediction selection unit 480 before reaching the IFU. Shah therefore discloses the use of different predictors and the selection between them to identify prediction information to be conveyed to the IFU. In other words, the information is not passed to the IFU until after the selection has happened. Consequently, there is no disclosure of flushing instruction addresses from a fetch queue as required by amended claim 1.”
Examiner first generally notes that Shah discloses information being passed to the IFU before the cited selection has occurred. For example, see paragraph [0101] as cited in the rejection. Examiner further notes that Shah was not relied upon to, by itself, disclose flushing instruction addresses from a fetch queue. Rather, the combination of prior art references as explained in the rejection was relied upon to render obvious the aforementioned subject matter.
Applicant on page 14 argues: ‘Additionally, paragraph [0111] of Shah refers to updating the BTC and discarding "instructions that may have been fetched". The use of the past tense clearly indicates that the discarding applies to items that have already been fetched. Shah does not disclose flushing instruction addresses from a fetch queue which is "configured to identify a sequence of instructions to be fetched for execution." Hence, there is no disclosure or suggestion of the claimed feature in Shah.’
However, Examiner notes that Shah was not relied upon to, by itself, disclose flushing instruction addresses from a fetch queue which is configured to identify a sequence of instructions to be fetched for execution. Rather, the combination of prior art references as explained in the rejection was relied upon to render obvious the aforementioned subject matter.
Applicant on pages 14-15 argues: ‘With reference to claim 1, the Office Action relies on paragraphs [0044] and [0046] of Lee. Paragraph [0044] of Lee states: "When an instruction is passed from the instruction cache to the decode stage 10, the corresponding prediction information stored in the fetch queue 68 for that instruction is used by post fetch correction circuitry 69, together with an initial pre-decoding of the instruction, to determine whether the contents of the fetch queue 68 have been correctly determined". The cited portion of Lee describes a determination as to whether a prediction was correct, rather than the performance of a "subsequent prediction" as claimed. For example, Figure 4 and paragraph [0047] of Lee describe how a prediction may be determined to be incorrect due to an inconsistency identified during the pre-decoding stage such as an unconditional branch being improperly predicted as not taken. This determination is based on the deterministic pre-decoding of an instruction, as referred to in paragraph [0044], and is therefore not a speculative prediction. For at least these reasons, the Office Action has provided no evidence to suggest that Lee discloses the claimed features.’
However, Examiner first notes that paragraph [0046] of Lee as cited discloses “a change to the prediction”, which corresponds to a subsequent prediction. Examiner also notes that paragraph [0044] as cited discloses a subsequent prediction (based on prediction information suggesting that a branch should have been taken) which is subsequent to an initial prediction entailing sequential fetch. Also see, for example, paragraph [0024] (“Since the prediction is made using a more accurate prediction it might be expected that such corrective action is less likely to result in a full pipeline flush being needed later”), paragraph [0025] (“a more accurate prediction”), paragraph [0028] (“In some situations, the post-fetch correction circuitry might perform an incorrect correction”), paragraph [0029] (“confidence value associated with whether the post-fetch correction circuitry would have previously correctly flushed the fetch queue”), [0051] (“improved prediction”), paragraph [0052] (“success rate of the post-fetch correction circuitry”), paragraph [0053] (“whether post-fetch correction is likely to be successful or not”) —each of these paragraphs reflect a subsequent speculative prediction rather than a definitive determination that a prediction is incorrect.
Regardless, Examiner notes that other prior art teaches a subsequent prediction, and even if Lee did not teach a subsequent prediction, such would not preclude the prior art combination from rendering obvious the claim. In addition, as explained in the rejection, while Examiner maintains that the combination of the first three prior art references renders obvious the claim language (e.g., the subject matter of the last four lines of the claim), Examiner has for the purposes of compact prosecution cited Lee to explicitly show the relevant subject matter being known to one of ordinary skill in the art before the effective filing date of the claimed invention.
Applicant across pages 15-16 argues that further prior art references relied upon in other claims do not rectify argued deficiencies.
However, as addressed above, Examiner maintains that there are no deficiencies associated with Shah and Lee.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
Prosecution Insights