DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1,4, 5, 7, 11, 114,15,17 rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without the term MEM, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). Claims recite various “MEM” including physical attributes MEM, OBJMEM, local MEM, however the term MEM is not defined in specifications nor is the term well know by one of ordinary skill in the art. For the purposes of examination, the term MEM is understood to mean memory.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gu et al (US 20200160593 A1)
Regarding claim 1, Gu discloses an application-specific integrated circuit (ASIC) ([0025] verse rendering training system), comprising:
a processing element (PE) array ([0025] processing units, one or more of the IRN);
a global ray-tracing scheduler (GRTS) in communication with the PE array ([0077] a scheduler unit);
a global memory access controller (GMAC) in communication with the PE array and the GRTS ([0077] high-bandwidth memory (HBM) subsystem,);
a physical attributes MEM (PAMEM) in communication with the GRTS ([0040] extracted properties include the albedo, the normal, the lighting, and glossiness); and
a reconfigurable mixed-precision processing element of the PE array configured to support an inverse rendering mode for background extraction and a ray-tracing mode ([0031] complex appearance effects provided by the RAR 110 may be simulated with a rendering equation via physically-based ray-tracing, which is non-differentiable).
Regarding claim 2, Gu discloses wherein, in the inverse rendering mode, the PE array is configured to perform physically based ray-tracing (PBRT) rendering for an augmented reality (AR) application ([0031] complex appearance effects provided by the RAR 110 may be simulated with a rendering equation via physically-based ray-tracing, which is non-differentiable).
Regarding claim 3, Gu discloses wherein the PBRT rendering comprises ray generation, intersect computation, light transportation effect, and shading ([0028] the direct illumination portion of the reconstructed image synthesized by the direct renderer 112, Id, is missing the more complex appearance effects (e.g., inter-reflection, cast shadows, near-field illumination, and realistic shading) that are included in the input image I and the reconstructed image Is).
Regarding claim 4, Gu discloses wherein the reconfigurable mixed-precision element of the PE array comprises a local processing element controller, a clock-gating control, a computing core, and a local OBJMEM memory ([0105] the scheduler unit 510 includes two dispatch units 515 that enable two different instructions from the same warp to be dispatched during each clock cycle).
Regarding claim 5, Gu discloses wherein the clock-gating control is configured to disable excessive computing units and local MEM ([0102] The scheduler unit 510 receives the tasks from the work distribution unit 325 and manages instruction scheduling for one or more thread blocks assigned to the SM).
Regarding claim 6, Gu discloses wherein each PE of the PE array comprises a PE compute unit configured for shading computation ([0027] The direct renderer 112 is a shading function which synthesizes the direct illumination contribution of the reconstructed image from the components predicted by the IRN 105.).
Regarding claim 7, Gu discloses wherein the PE compute unit is configured to receive data from both the PAMEM and the local OBJMEM memory ([0111] Each SM 440 also comprises N LSUs 554 that implement load and store operations between the shared memory/L1 cache 570 and the register file 520.).
Regarding claim 8, Gu discloses wherein the computing core supports a division module ([0110] Each SM 440 also comprises M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like)).
Regarding claim 9, Gu discloses wherein the computing core supports a square root operations module ([0110] Each SM 440 also comprises M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like)).
Regarding claim 10, Gu discloses wherein, in the ray-tracing mode, the reconfigurable mixed- precision element of the PE array is configured to perform a scalable 3D model partitioning flow ([0107] Each core 550 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit).
Regarding claim 11, Gu discloses A mobile device ([0129] a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device), comprising:
application-specific integrated circuit (ASIC) ([0025] verse rendering training system), comprising:
a processing element (PE) array ([0025] processing units, one or more of the IRN);
a global ray-tracing scheduler (GRTS) in communication with the PE array ([0077] a scheduler unit);
a global memory access controller (GMAC) in communication with the PE array and the GRTS ([0077] high-bandwidth memory (HBM) subsystem,);
a physical attributes MEM (PAMEM) in communication with the GRTS ([0040] extracted properties include the albedo, the normal, the lighting, and glossiness); and
a reconfigurable mixed-precision processing element of the PE array configured to support an inverse rendering mode for background extraction and a ray-tracing mode ([0031] complex appearance effects provided by the RAR 110 may be simulated with a rendering equation via physically-based ray-tracing, which is non-differentiable).
Regarding claim 12, Gu discloses wherein, in the inverse rendering mode, the PE array is configured to perform physically based ray-tracing (PBRT) rendering for an augmented reality (AR) application ([0031] complex appearance effects provided by the RAR 110 may be simulated with a rendering equation via physically-based ray-tracing, which is non-differentiable).
Regarding claim 13, Gu discloses wherein the PBRT rendering comprises ray generation, intersect computation, light transportation effect, and shading ([0028] the direct illumination portion of the reconstructed image synthesized by the direct renderer 112, Id, is missing the more complex appearance effects (e.g., inter-reflection, cast shadows, near-field illumination, and realistic shading) that are included in the input image I and the reconstructed image Is).
Regarding claim 14, Gu discloses wherein the reconfigurable mixed-precision element of the PE array comprises a local processing element controller, a clock-gating control, a computing core, and a local OBJMEM memory ([0105] the scheduler unit 510 includes two dispatch units 515 that enable two different instructions from the same warp to be dispatched during each clock cycle).
Regarding claim 15, Gu discloses wherein the clock-gating control is configured to disable excessive computing units and local MEM ([0102] The scheduler unit 510 receives the tasks from the work distribution unit 325 and manages instruction scheduling for one or more thread blocks assigned to the SM).
Regarding claim 16, Gu discloses wherein each PE of the PE array comprises a PE compute unit configured for shading computation ([0027] The direct renderer 112 is a shading function which synthesizes the direct illumination contribution of the reconstructed image from the components predicted by the IRN 105.).
Regarding claim 17, Gu discloses wherein the PE compute unit is configured to receive data from both the PAMEM and the local OBJMEM memory ([0111] Each SM 440 also comprises N LSUs 554 that implement load and store operations between the shared memory/L1 cache 570 and the register file 520.).
Regarding claim 18, Gu discloses wherein the computing core supports a division module ([0110] Each SM 440 also comprises M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like)).
Regarding claim 19, Gu discloses wherein the computing core supports a square root operations module ([0110] Each SM 440 also comprises M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like)).
Regarding claim 20, Gu discloses wherein, in the ray-tracing mode, the reconfigurable mixed- precision element of the PE array is configured to perform a scalable 3D model partitioning flow ([0107] Each core 550 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIVANG I PATEL whose telephone number is (571)272-8964. The examiner can normally be reached on M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571) 272-2330. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHIVANG I PATEL/Primary Examiner, Art Unit 2615
Prosecution Insights