DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (KR10-2021-0102561 Republic of Korea 08/04/2021).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 02/14/2025, 06/18/2025, 12/24/2025, 04/23/2026, 07/06/2026, 07/24/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings submitted on 02/14/2025. These drawings are review and accepted by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al (US 10,679,700 B2 hereinafter “Shibata”) in view of Baek et al (US 10,636,492 B2 hereinafter “Baek”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Shibata, for example in Figs. 1-47, discloses a method of operating (e.g., program operation; in Figs. 40, 43 related in Figs. 1-39, 41-42, 44-47) a semiconductor memory device (e.g., memory device 1; in Fig. 2 related in Figs. 1, 3-47) performing a program operation on a source select transistor of a memory block (e.g., memory block 100; in Fig. 2 related in Figs. 1, 3-47) including a plurality of string groups (e.g., memory strings within SU0-SU2; in Figs. 5, 12, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47), the plurality of string groups (e.g., groups; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47) each including at least one cell string (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47), the at least one cell string including inner source select transistors (e.g., SGS0-SGS1; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47) located adjacent to memory cells (e.g., MC; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47) and outer source select transistors (e.g., SGS2-SGS3; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47) located adjacent to a common source line (e.g., SL; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47), the method comprising: performing a program operation on the outer source select transistors (implied the programmed source-side select transistors; in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47; see Col. 27, lines 18-19+).
However, Shibata is silent with regard to the performing a program operation on the inner source select transistors by applying a plurality of program voltages to gates of the inner source select transistors a plurality of times, wherein the performing of the program operation on the inner source select transistors comprises performing a verify operation by dividing the inner source select transistors into at least two groups.
In the same field of endeavor, Baek, for example in Figs. 1-13, discloses the performing a program operation on the inner source select transistors by applying a plurality of program voltages to gates of the inner source select transistors a plurality of times (by using incremental step pulse program ISPP; in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13; See Col. 2, lines 4-9+), wherein the performing of the program operation on the inner source select transistors comprises performing a verify operation by dividing the inner source select transistors into at least two groups (see for example in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13).
t would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shibata such as a semiconductor memory device includes the memory strings having a plurality of memory cells (see for example in Figs. 1-47 of Shibata) by incorporating the teaching of Baek such as memory device having plurality of memory cell strings, plurality of source select transistors and plurality of drain select transistors (see for example in Figs. 1-13 of Baek), for the purpose of controlling the source select transistors coupled to the first source select line may be programmed using a program voltage having a fixed voltage level, and the source select transistors coupled to the second source select line may be programmed using an ISPP method, so that a program operation on the source select transistors coupled to the second source select line may be efficiently performed (see Baek discloses).
Regarding claim 2, the above Shibata/Baek, combination discloses wherein the plurality of string groups include first, second, third, and fourth string groups, wherein an inner source select transistor in the first string group and an inner source select transistor in the second string group are commonly coupled to a first inner source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an inner source select transistor in the third string group and an inner source select transistor in the fourth string group are commonly coupled to a second inner source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an outer source select transistor in the first string group and an outer source select transistor in the second string group are commonly coupled to a first outer source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an outer source select transistor in the third string group and an outer source select transistor in the fourth string group are commonly coupled to a second outer source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), and wherein performing the program operation on the outer source select transistors comprises: applying a turn-on voltage to first to fourth drain select lines coupled to the first to fourth string groups, respectively, and applying a program pass voltage to the first and second inner source select lines and word lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying a program voltage to the first and second outer source select lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 3, the above Shibata/Baek, combination discloses wherein applying the program voltage to the first and second outer source select lines comprises applying the program voltage to the first and second outer source select lines a predetermined number of times (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 4, the above Shibata/Baek, combination discloses wherein the plurality of string groups includes first, second, third, and fourth string groups, wherein an inner source select transistor in the first string group and an inner source select transistor in the second string group are commonly coupled to a first inner source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an inner source select transistor in the third string group and an inner source select transistor in the fourth string group are commonly coupled to a second inner source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an outer source select transistor in the first string group and an outer source select transistor in the second string group are commonly coupled to a first outer source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), wherein an outer source select transistor in the third string group and an outer source select transistor in the fourth string group are commonly coupled to a second outer source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), and wherein performing the program operation on the outer source select transistors comprises: applying a turn-on voltage to first to fourth drain select lines coupled to the first to fourth string groups, respectively, and applying a program pass voltage to word lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying a program voltage to the first and second outer source select lines and the first and second inner source select lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 5, the above Shibata/Baek, combination discloses wherein applying the program voltage to the first and second inner source select lines and the first and second outer source select lines comprises applying the program voltage to the first and second inner source select lines and the first and second outer source select lines a predetermined number of times (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 6, the above Shibata/Baek, combination discloses wherein performing the program operation on the inner source select transistors comprises a plurality of program loops, and one of the plurality of program loops (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above) comprises: setting states of first to fourth drain select lines and first to fourth bit lines coupled to first, second, third, and fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above), respectively; applying a program pass voltage to word lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a turn-off voltage to first and second outer source select lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a program voltage to first and second inner source select lines; and performing the verify operation on the inner source select transistors included in the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 7, the above Shibata/Baek, combination discloses wherein performing the verify operation on the inner source select transistors included in the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above) comprises: verifying the inner source select transistors included in the first and third string groups, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and verifying the inner source select transistors included in the second and fourth string groups, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 8, the above Shibata/Baek, combination discloses wherein performing the verify operation on the inner source select transistors included in the first and third string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above) comprises: setting a voltage of the common source line and a voltage of bit lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a turn-on voltage to the first and second outer source select lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying the turn-on voltage to drain select lines coupled to the first and third string groups and the turn-off voltage to drain select lines coupled to the second and fourth string groups; applying a verify pass voltage to the word lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying a verify voltage to the first and second inner source select lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 9, the above Shibata/Baek, combination discloses wherein setting the voltage of the common source line and the voltage of the bit lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above) comprises: applying a ground voltage to the common source line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a first voltage greater than the ground voltage to the bit lines coupled to the first and third string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying the ground voltage to the bit lines coupled to the second and fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 10, the above Shibata/Baek, combination discloses wherein performing the verify operation on the inner source select transistors included in the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above) comprises: verifying the inner source select transistors included in the first string group, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); verifying the inner source select transistors included in the second string group, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); verifying the inner source select transistors included in the third string group, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and verifying the inner source select transistors included in the fourth string group, among the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 11, the above Shibata/Baek, combination discloses wherein performing the verify operation of the inner source select transistors included in the first string group comprises: setting a voltage of the common source line and a voltage of bit lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a turn-on voltage to the first outer source select line and the turn-off voltage to the second outer source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying the turn-on voltage to a drain select line coupled to the first string group and the turn-off voltage to drain select lines coupled to the second to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a verify pass voltage to the word lines (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying a verify voltage to the first inner source select line and the turn-off voltage to the second inner source select line (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 12, the above Shibata/Baek, combination discloses wherein setting the states of the first to fourth drain select lines and the first to fourth bit lines coupled to the first to fourth string groups, respectively, comprises: applying a program inhibition voltage to a bit line coupled to a string group verified completely in a previous program loop (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a program permission voltage to a bit line coupled to a string group not verified completely in the previous program loop (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying a turn-on voltage to drain select lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 13, the above Shibata/Baek, combination discloses wherein setting the states of the first to fourth drain select lines and the first to fourth bit lines coupled to the first to fourth string groups, respectively, comprises: applying a program permission voltage to bit lines coupled to the first to fourth string groups (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); applying a turn-on voltage to a drain select line coupled to a string group not verified completely in a previous program loop (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above); and applying the turn-off voltage to a drain select line coupled to a string group verified completely in the previous program loop (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Regarding claim 14, the above Shibata/Baek, combination discloses further comprising performing a soft erase operation on the outer source select transistors included in the first to fourth string groups when verification of the inner source select transistors of all string groups is completed (see for example in Figs. 5, 15, 17-18, 20, 24-25, 27 related in Figs. 1-4, 6-11, 13-14, 16, 19, 21-23, 26, 28-47 of Shibata and also see in Figs. 3-4, 9 related in Figs. 1-2, 5-8, 10-13 of Baek, as discussed above).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 09/29/2026
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