DETAILED ACTION
The action is responsive to the following communications: the Application filed February 14, 2025, and the information disclosure statement (IDS) filed February 21, 2025. This application is a CON of 17/675,447.
Claims 1-20 are pending. Claims 1, 9 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 21, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,260,914. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,260,914
Comment
Claim 1. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
determining that a condition associated with the memory cell is satisfied; and
executing a level shifting operation associated with the memory cell in response to the condition being satisfied.
Claim 1. A memory device comprising:
a memory array comprising a plurality of memory cells
configured as a multi-level cell (MLC) memory; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a set of memory cells of the memory array to be programmed during a programing operation;
causing, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to
a first programing level of a set of programming levels, wherein the first programming pulse programs
each programing level of the set of programming levels associated with the set of memory cells;
performing a program verify operation corresponding
to the first programing level;
comparing a threshold voltage of the memory cell to one or more program verify voltage levels of the
program verify operation to determine whether a condition is satisfied; and
executing a level shifting operation in response to the condition being satisfied, wherein the level shifting
operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 9-10, 14-15, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (US 2019/0371417).
Regarding independent claims 1, 9 and 14, Hsieh et al. disclose a memory device comprising:
a memory array comprising a plurality of memory cells (para. 0002: flash memory , along with FIG. 6); and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the programming pulse programs each programming level of the set of programming levels associated with the set of memory cells (e.g., FIGS. 1-2: P(n) and accompanying disclosure);
determining that a condition associated with the memory cell is satisfied (FIGS. 1-2: VR2, VR1); and
executing a level shifting operation associated with the memory cell in response to the condition being satisfied (see FIG. 1: 130 and FIG. 2: loops) (see each embodiment of FIGS. 1-3, FIGS. 4-6 and FIGS. 7-9, and accompanying disclosure).
Regarding claims 2, 10 and 15, which depends from claims 1, 9 and 14, respectively, Hsieh et al. disclose the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and less than a second program verify voltage level (see e.g., FIG. 2, VR2 and VR1).
Further, it is an inherent flash memory characteristics that performing multiple program verify operations because programming condition is passed when the threshold voltage of the programmed memory cell is between failed and passed verify voltage levels.
Regarding claims 4 and 17, which depends from claims 1 and 14, respectively, Hsieh et al. disclose the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and a second program verify voltage level and less than a third program verify voltage level of one or more program verify voltage levels of a program verify operation (see e.g., FIG. 2, VR2 and VR1).
Further, it is an inherent flash memory characteristics that performing multiple program verify operations because programming condition is passed when the threshold voltage of the programmed memory cell is between failed and passed verify voltage levels.
Regarding claims 6 and 19, which depends from claims 1 and 14, respectively, Hsieh et al. disclose the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted (see para. 0020: … the bias voltage on the bit line is 0V, then … If the bias voltage on the bit line is the power source …).
Further, it is an inherent flash memory characteristics that multiple bit line voltages to the memory cells.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5 and 7-8, 11-13, 16, 18 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 2019/0371417) in view of Huang et al. (US 2021/0350853).
Regarding claims 3, 11 and 16, Hsieh et al. teach the limitations of claims 2, 10 and 15, respectively.
Hsieh et al. further teach wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level (see e.g., FIG. 2).
Hsieh et al. are silent with respect to a second programming level that is lower than the first programming level.
Huang et al. teach the deficiencies in FIG. 3A and accompanying disclosure.
Hsieh et al. and Huang et al. are analogous art because they both are directed to flash memory and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Huang et al. to the teaching of Hsieh et al. such that a flash memory, as taught by Hsieh et al., utilizes decreased programming pulse, as taught by Huang et al., for the purpose of making programming voltage pulse to be less in compare to increased programming pulses, thereby utilizing a variety of program-verify iterations.
Regarding claims 5 and 18, Hsieh et al. teach the limitations of claims 4 and 17, respectively.
Hsieh et al. further teach wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is more than one programming level (see e.g., FIG. 2).
Hsieh et al. are silent with respect to a second programming level that is lower than the first programming level.
Huang et al. teach the deficiencies in FIG. 3A and accompanying disclosure.
Hsieh et al. and Huang et al. are analogous art because they both are directed to flash memory and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Huang et al. to the teaching of Hsieh et al. such that a flash memory, as taught by Hsieh et al., utilizes decreased programming pulse, as taught by Huang et al., for the purpose of making programming voltage pulse to be less in compare to increased programming pulses, thereby utilizing a variety of program-verify iterations.
Regarding claims 7 and 12, Hsieh et al. teach the limitations of claims 1 and 9, respectively.
Hsieh et al. further teach the condition is satisfied when a threshold voltage of the memory cell is less than a first program verify voltage level associated with a second programming level (see e.g., FIG. 2).
Hsieh et al. are silent with respect to a second programming level that is lower than the first programming level.
Huang et al. teach the deficiencies in FIG. 3A and accompanying disclosure.
Hsieh et al. and Huang et al. are analogous art because they both are directed to flash memory and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Huang et al. to the teaching of Hsieh et al. such that a flash memory, as taught by Hsieh et al., utilizes decreased programming pulse, as taught by Huang et al., for the purpose of making programming voltage pulse to be less in compare to increased programming pulses, thereby utilizing a variety of program-verify iterations.
Regarding claims 8 and 13, Hsieh et al. and Huang et al., as combined, teach the limitations of claims 7 and 12, respectively.
Hsieh et al. further teach executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is higher than the first programming level (FIG. 2).
Regarding claim 20, Hsieh et al. teach the limitations of claim 14.
Hsieh et al. further teach the condition is satisfied when a threshold voltage of the memory cell is less than a first program verify voltage level associated with a second programming level that is lower than the first programming level; and wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is higher than the first programming level (see e.g., FIG. 2).
Hsieh et al. are silent with respect to a second programming level that is lower than the first programming level.
Huang et al. teach the deficiencies in FIG. 3A and accompanying disclosure.
Hsieh et al. and Huang et al. are analogous art because they both are directed to flash memory and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Huang et al. to the teaching of Hsieh et al. such that a flash memory, as taught by Hsieh et al., utilizes decreased programming pulse, as taught by Huang et al., for the purpose of making programming voltage pulse to be less in compare to increased programming pulses, thereby utilizing a variety of program-verify iterations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 9 and 14, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights