DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 17.
b. Pending: 1-20.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 7-17, 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,254,950. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 is rejected over claims 5 and 8 of parent 12,254,950.
Claim 2 is rejected over claims 1, 2 or 8, 9 of parent 12,254,950.
Claims 3, 12 are rejected over claims 3 or 10 of parent 12,254,950.
Claims 4, 13 are rejected over claim 6 of parent 12,254,950.
Claims 5, 14 are rejected over claims 2 or 9 of parent 12,254,950.
Claim 7 is rejected over claims 1 and 5 of parent 12,254,950.
Claim 8 is rejected over claims 4 and 11 of parent 12,254,950.
Claims 9, 15 are rejected over claim 7 of parent 12,254,950.
Claims 10, 16 are rejected over claims 1, 4 and 5 of parent 12,254,950.
Claim 11 is rejected over claims 1 and 5 of parent 12,254,950.
Claim 17 is rejected over claims 5 and 8 of parent 12,254,950.
Claim 19 is rejected over claims 1, 5, 6 of parent 12,254,950.
Claim 20 is rejected over claims 3, 10 of parent 12,254,950.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu PG PUB 20230350606 (hereinafter Hsu), in view of Schuetz PG PUB 20130094271 (hereinafter Schuetz).
Regarding independent claim 1, Hsu teaches an enable pin configuration method of a semiconductor package structure, wherein the semiconductor package (figure 9 of Hsu, [0098] of Hsu, “…the multiple memory dies 104 can be grouped into a set of memory packages…Each memory package may include one or more memory dies 104 in communication with storage controller 102…”) structure comprises N dies (902/904 in figure 9 of Hsu, [0176]-[0177] of Hsu, “…FIG. 9 depicts memory system 900 having multiple memory arrays 902 and 904… a group of memory dies or a memory array may refer to one or more memory dies… embodiments herein may include three, four, five, or any number of groups of memory dies…”), N is a positive integer greater than or equal to 2, and the method comprises:
receiving at least one control command of M dies of the N dies, wherein M is a positive integer greater than or equal to 1, and M is less than or equal to N (figure 12 of Hsu teaches the first group G1 perform command/address sequencing responsive to a host command, [0176]-[0177] of Hsu, [0203] of Hsu, “…the first group G1 may be instructed to perform command/address sequencing 1236 on the test interface, for example, responsive to a command from a host device to perform another data operation…”, thus this “one die in G1” in figure 12 correspond to the claimed M dies);
in response to the at least one control command (host command, [0203] of Hsu, “…responsive to a command from a host device… the storage controller asserts SKENn_G1 signal 1204 to logic LOW level, to notify the first group G1 of memory dies that command/address sequencing is enabled…”), generating an address information of at least one of the M dies ([0184] of Hsu, “…the storage controller generates a mode select signal encoded with a first bit pattern to instruct the memory die 910 to enter a one of CLE or ALE mode…the storage controller 930 generates a command or address data signal encoded with a second bit pattern that is one of a command code and an address code…”; and
sending the address information of at least one of the M dies ([0173] of Hsu, [0187] of Hsu, figure 6 of Hsu, figure 9-11 of Hsu, Hsu teaches that generated address data signal is transmitted from storage controller 930 to memory die 920 over the test data bus/X1DQ signal, Hsu also teaches that an address code stored in address register 668 can be transmitted from the memory die back to the storage controller), wherein the address information is configured to address an enable signal provided by the enable pin (Hsu teaches that the address code can include die selection, while the respective memory dies receive enable signals such as SKENn through corresponding enable pins. SKENn is an enable signal that enables command/address sequencing on the memory die. Figure 9 teaches memory die 910 include SKENn pin 918 and memory die 920 include SKENn pin 928; these SKENn_G1 and SKENn_G2 signals are associated with the respective groups of memory dies. Hsu then transmits the command/address information, including die-selection information, to the enabled die).
Alternatively, for argument sake, let us assume that Hsu is not as explicit that the address information itself is used to distinguish individual dies sharing the same enable pin.
Schuetz teaches precisely that missing relationship. Schuetz teaches a plurality of semiconductor memory device sharing a serial enable signal, with the controller adding the device identifier of a targeted device to an address field of a command so that an individual device can be addressed without requiring a separate chip-enable pin for each device ([0018] of Schuetz, “…there is one enable signal output from the controller which is connected serially to all memory devices on the channel…”, [0021], “…By utilizing an additional address field in each command, i.e., comprising a device ID, the need for a controller having a unique chip-enable enable output signal is removed. Thus the controller requires only one enable output pin per channel rather than a separate enable output pin for each memory device in a channel, thereby reducing the per-channel pin-count…”). Thus the device-ID address information logically identifies the individual device while the devices share the enable signal from the single enable pin.
It would have been obvious to one of ordinary skill in the art to employ Schuetz’device -identifier/address-field selection technique in Hsu’s multi-die memory package, thereby permitting multiple memory dies to share an enable signal while remaining individual addressable. The advantage of doing so is “reducing the per-channel pin-count” ([0021] of Schuetz).
Regarding independent claim 10, claim 10 recites apparatus subject matter corresponding to the method recited in claim 1. Hsu teaches a memory device 200 including storage controller 102 and a plurality of memory dies 104a-104n.
Regarding independent claim 17, claim 17 recites memory system comprising a controller and at least one memory device coupled with the controller, wherein the memory device comprises the semiconductor package subject matter recipes in claim 10. Thus claim 17 is rejected for the same reason set forth above with respect to claims 1 and 10.
Regarding claim 18, the combination of Hsu and Schuetz teaches the memory system of claim 17, further comprising a printed circuit board (PCBI) coupled with the memory device and the controller, wherein the PCB is configured to connect each enable pin of the M dies to one enable pin of the controller (Schuetz teaches use of a single enable output from the controller for a plurality of memory device. Schuetz teaches in [0021] that the use of the device identifier permits the controller to require “the controller requires only one enable output pin per channel rather than a separate enable output pin for each memory device in a channel, thereby reducing the per-channel pin-count”. Schuetz also expressly teaches the physical interconnection and PCB implementation, explaining that high pin counts increase printed circuit board (PCB) complexity and that the associated interconnections are implemented as traces/interconnections in the system, [0006] of Schuetz, “…High pin counts increase printed circuit board (PCB) complexity and drive up the cost of the controllers...” Under BRI, the claimed PCB “configured to connect each enable pin of the M dies to one enable pin of the controller” does not require each die enable input to be directly connected by an independent trace to the controller pin. Schuetz ‘s serial enable link connects the plurality of device enable inputs, through the serial enable path, to the controller’s single enable output. It would have been obvious to implement the Hsu/Schuetz memory -controller and memory die interconnections on a PCB, as taught hy Schuetz, in order to provide a known physical electrical interconnection between the controller and memory devices while retaining Schuetz reduce-pin architecture).
Claim 2-9, 11-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu PG PUB 20230350606 (hereinafter Hsu), in view of Schuetz PG PUB 20130094271 (hereinafter Schuetz), further in view of PYEON PG PUB 20090198857 (hereinafter PYEON).
Regarding claim 2, the combination of Hsu and Schuetz teaches the method of claim 1, but does not teach wherein the generating the address information of at least one of the M dies comprises:
generating an indication information of at least one of the M dies based on the at least one control command; generating an encoded information of at least one of the M dies based on the indication information; and decoding the encoded information to obtain the address information of at least one of the M dies.
However, PYEON teaches a memory controller that, based on a host command, determines which memory devices are selected and supplied the ID numbers or addresses of the selected memory devices to mask encoder 800 (figure 7A, 8 and [0063]-[0067]). Thus, the selected device ID number/addresses correspond to the claimed indication information generated based on the control command.
PYEON further teaches mask encoder 800 encoding the selected memory-device ID number/addresses into code information, including a mask code and Target ID (figure 7A, 7B and 0, [0064]-[0069]). The target ID is one of the selected device addresses, and the mask code is generated based on the selected device addresses. This code information corresponds to the claimed encoded information.
Pyeon further teaches decoding/processing that encoded code information at the memory device. ID processor 1210 receives the mask code and Target ID. ID match decoder 1232 performs decoding operations using the device ID, mask code, and Target ID, and adder 1230 and last ID decoder 1234 processes the encoded information to produce/determine a particular designated memory-device address (figures 12-13, [0078]-[0087]). In particular, adder 1230 produces the address of the last designated memory device from the mask code and Target ID. Therefore, Pyon teaches generating an indication information of at least one of the M dies based on the at least one control command (Pyeon teaches selected device ID/address information produced responsive to the host command); generating an encoded information of at least one of the M dies based on the indication information (Pyeon teaches mask encoder 800 generates the mask code/Target-ID code information based on the selected device IDs); and decoding the encoded information to obtain the address information of at least one of the M dies (ID processor 1210, ID match decoder 1232, adder 1230, and last-ID decoder 1234 process the code information to determine a designated device ID/address).
It would have been obvious to one of ordinary skill in the art to incorporate Pyeon’s known device-address encoding and decoding arrangement into the Hsu/Schuetz multi-memory -die system because Schuetz already teaches identifying individual memory devices while sharing a single enable arrangement, and Pyeon provide a known techniques for encoding addresses of selected device into code information and decoding that information for device selection. Such a medication would permit scalable identification and selection of one or more memory dies while retraining the reduced enable pin architecture of Schuetz. Schuetz seeks reduced per channel pin count, while Pyeon is directed to selecting subsets of serially connected memory device.
Regarding claim 3, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 2, wherein the method further comprises setting a first numerical value in a register of at least one of the M dies to be a second numerical value, and the second numerical value of at least one of the M dies corresponds to the encoded information of at least one of the M dies (Pyeon command parser receives the encoded code information and stores the mask code in mask register 1226 and the Target ID in Target ID register 1228 (figure 12, [0081]-[0083]). Under BRI, loading a received numerical mask-code or Target-ID value into the corresponding register constitutes setting the pre-existing register value to the newly received numerical value, and that newly stored numerical value directly corresponds to the encoded information generated by mask encoder 800).
Regarding claim 4, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 2, wherein when M is greater than or equal to 2, the encoded information of each of the M dies is different (Pyeon teaches that, when multiple memory devices are selected, the encoded information corresponding to the respective devices may be different. Pyeon teaches in figure 10B and [0075] describe four selected addresses for which the corresponding coded ID numbers are, address 1 corresponds to 1101, while address 2 corresponds to 1100. Thus when M is at least two, Pyeon demonstrates different encoded values corresponding to different selected memory devices).
Regarding claim 5, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 2, wherein a peripheral circuit of each of the M dies comprises a control circuit, a trigger, a first decoding circuit, and a second decoding circuit, which are coupled in sequence (Hsu teaches the peripheral circuit implementation. Hsu teaches a memory die having a die controller/control circuitry and decoding circuitry, including die controller 204/control circuitry 214, decoder circuit 216, and address decoder 218. Hsu further teaches the test-controller/latching circuitry responsive to SKENn/SKn signaling for receiving and propagating the mode/indication information, see Hsu figure2A, 6-7 and 14, [0063]-[0066], [0131], [0145]-[0149], [0217]-[0222], thus Hsu teaches structural stages corresponding to control circuit[Wingdings font/0xE0]trigger[Wingdings font/0xE0]first decoding circuit[Wingdings font/0xE0]second decoding circuit, while Pyeon teaches the address-information encoding/decoding operation discussed in claim 2), and the method further comprises: receiving, by the control circuit, the at least one control command; generating, by the control circuit, the indication information based on the at least one control command; sending, by the control circuit, the indication information; receiving, by the trigger, the indication information; sending, by the trigger, the indication information to the first decoding circuit; generating, by the first decoding circuit, the encoded information of at least one of the M dies based on the indication information; and decoding, by the second decoding circuit, the encoded information to obtain the address information of at least one of the M dies (Hsu teaches receiving control information, sampling /latching the indication information, decoding a first bit pattern to identify a selected mode, and decoding a subsequent encoding bit pattern to obtain an address code. Hsu specifically teaches that a bit pattern may be decoded to obtain an address code and that the address code is then supplied to the address decoding circuitry).
Regarding claim 6, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 2, wherein the encoded information of each of the M dies comprises 4 bits or 8 bits, and the address information of each of the M dies comprises 1 bit or 4 bits (Pyeon teaches in figure 7B and [0065] a device address sub-field comprising a mask code portion and Target-ID portion that are collectively one byte, e.g., 8 bits. Pyeon teaches four bit device ID/address values and four bit mask code, see figure 7B, 9, 13).
Regarding claim 7, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 1, wherein M is less than or equal to N, and a value of N includes 2, 4 or 8 (Pyeon teaches a system containing a plurality of memory devices from which a subset M is selected. For example, figure 2A teaches four memory devices 24, 26, 28, 30 and Pyeon explains that alternative embodiments may contain any suitable number of memory devise, [0042], “…current example of FIG. 2A includes four memory devices, but alternate embodiments can include a single memory device, or any suitable number of memory devices...” Pyeon further teaches selecting one, all or two or more devices from the available plurality, [0063]-[0068] of Pyeon).
Regarding claim 8, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 1, wherein a value of M includes 1, 2, 4, 8, 16 or 32 (Pyeon teaches in figure 2A, 7A-10B, [0042], [0063]-[0069] that mask encoder can be scaled for two, eight, and any number of ID numbers and teaches a sixteen-device implementation).
Regarding claim 9, the combination of Hsu, Schuetz and Pyeon teaches the method of claim 2, wherein each of the M dies include a target die, and the method further comprises: receiving at least one chip selection signal of the target die, wherein the at least one chip selection signal comprises the address information of the target die; and receiving the enable signal of the target die based on the at least one chip selection signal (Pyeon teaches in figure 7A-8 an d[0063]-[0067] identifying a particular selected or target memory device using a unique ID/device address. The controller determines selected devices and transmits a Target ID/device-address value as part of the command information. Scheutz teaches a command used to select an individual target device, wherein an address field of the command contains the device, together with the shared serial enable arrangement. Each memory device extracts the device identifier and determines whether it matches its assigned identifier. The matching target device participates in the transaction. See Schuetz [0019]-[0023], [0071]-[0073], figure 3-6, Schuetz also teaches a signal serial enable signal for enabling the plurality of memory device. Under BRI, the address-bearing command/identification signal constitute the claimed chip selection signal).
Regarding claim 11, claim 11 recites subject matter corresponding to that recites in claim 2, thus claim 11 is rejected for the same reason set forth above with respect to claim 2.
Regarding claim 12, claim 12 recites subject matter corresponding to that recites in claim 3, thus claim 12 is rejected for the same reason set forth above with respect to claim 3.
Regarding claim 13, claim 13 recites subject matter corresponding to that recites in claim 4, thus claim 13 is rejected for the same reason set forth above with respect to claim 4.
Regarding claim 14, claim 14 recites subject matter corresponding to that recites in claim 5, thus claim 14 is rejected for the same reason set forth above with respect to claim 5.
Regarding claim 15, claim 15 recites subject matter corresponding to that recites in claim 9, thus claim 15 is rejected for the same reason set forth above with respect to claim 9.
Regarding claim 16, claim 16 recites subject matter corresponding to that recites in claim 7 and 8, thus claim 16 is rejected for the same reason set forth above with respect to claim 7 and 8.
Regarding claim 19, claim 19 recites subject matter corresponding to that recites in claims 2 and 4, thus claim 19 is rejected for the same reason set forth above with respect to claims 2 and 4.
Regarding claim 20, claim 20 recites subject matter corresponding to that recited in claim 3, thus claim 20 is rejected for the same reason set forth above with respect to claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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