DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/13/2025. Claims 1-20 are pending in the Application, of which Claims 1, 18 and 20 are independent.
Continuity Priority information
The present Application 19054497 filed 02/14/2025 Claims Priority from Provisional Application 63555247, filed 02/19/2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tian et al. (PgPub. US 20230420053) Pub. Date: 2023-12-28.
Regarding independent Claims 1, 18 and 20, Tian discloses techniques for checking vulnerability to cross-temperature read errors in a memory device, comprising:
a set of memory components of a memory sub-system; and at least one processing device, configured to perform operations. [0052] FIG. 1A. The memory device 100 may include one or more memory die 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read/write circuits 128. [0061] The storage device(s) 122a, 122b comprise, code such as a set of instructions, and the processor 122c is operable to execute the set of instructions to provide the functionality described herein.
performing a first program-erase (PE) cycle on the individual portion; and performing a second PE cycle on the individual portion;
[0120] FIG. 16 is an example embodiment of an erase operation. At step 1600, a command to erase a memory block is received by the memory device, and the memory cells in memory block “Block n” are erased. At step 1602, a program-erase Cycle Count of the memory cells of Block n is determined.
determining that an individual portion of the set of memory components satisfies a degradation criterion; and selectively retiring the individual portion based on results.
[0122] If the answer at decision step 1604 is “yes,” then at step 1606, the cross-temperature checking operation begins. That is, a group of memory cells (for example, the memory cells of one or more word lines) in Block n are programmed in one or more programming loops while all special device modes are disabled (for example, quick-pass write, program verify, smart verify, etc.) to obtain the nVt distribution. The nVt width of the group of memory cells is then analyzed, and a judgment operation involves comparing the nVt width to predetermined thresholds.
[0123] At decision step 1608, it is determined if Block n failed the cross-temperature checking operation. If the answer at decision step 1608 is “yes,” “satisfies degradation criterion” then at step 1610, the memory block is either retired “retiring” or is switched to SLC operation for the remainder of its operating life.
Regarding Claims 2, 12-14, 19, Tian discloses determining that the individual portion satisfies the degradation criterion. [0125] At step 1606, for example, in one embodiment, the selected word line is WL79. The nVt judgment operation involves measuring the nVt width of the memory cells of WL79 and comparing the nVt width to a first predetermined threshold, which may be established experimentally. If the nVt width is less than the first predetermined threshold, then the memory block passes the cross-temperature checking operation. If the nVt width is greater than the first predetermined threshold, then the memory block fails the cross-temperature checking operation, thus corresponding to the “degradation criterion”.
Regarding Claims 3-6, Tian discloses determining that the reliability of the first group of regions and the second group of regions represents failure; [0132] FIG. 18, shows a plot of cross-temperature sensing operations applied to a plurality of word lines in memory blocks at four different program and erase cycle amounts. As illustrated, zero or very few memory blocks at one and three hundred cycles failed the cross-temperature sensing operation. More memory blocks at one thousand cycles failed the cross-temperature sensing operation, and even more memory blocks at three thousand cycles failed the cross-temperature sensing operation. By allowing the memory device to detect when a memory block becomes vulnerable to cross-temperature read errors, the techniques provided in the present disclosure may protect data by reducing UECC errors.
Regarding Claims 7, 8, Tian discloses the individual portion comprises an individual block stripe; [0089] FIG. 6B illustrates an example cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3 of FIG. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers and four dummy word line layers DWLD0, DWLD1, DWLS0 and DWLS1, in addition to data word line layers (word lines) WL0-WL111.
Regarding Claims 9-11, Tian discloses placing the individual portion in a free block pool to allow data to be written to the individual portion in response to applying the memory operation on the first group of regions to test reliability of the first group of regions; [0107] FIG. 11 depicts a waveform 1100 of an example memory cell programming operation for programming the memory cells TLC. As depicted, each program loop includes a programming pulse VPGM and one or more verify pulses, depending on which data states are being programmed in a particular program loop. A square waveform is depicted for each pulse for simplicity; however, other shapes are possible, such as a multilevel shape or a ramped shape.
Regarding Claims 15-17, Tian discloses storing a table that associates each of the plurality of groups with a respective PE cycle count. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, if a programming operation is completed. [0059] For example, FIG. 1B is a block diagram of an example control circuit 150 which comprises a programming circuit 151, a counting circuit 152, and a determination circuit 153.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: July 28, 2026
Non-Final Rejection 20260728
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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