DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Diard (US 7,383,412).
Referring to claims 1, 8 and 15, Diard discloses a method (fig. 4, on-demand memory synchronization process 400) comprising:
acquiring a first lock (fig. 3, lock command 304; 13:59-14:12, current_count) within a first memory context (fig. 3, memory access 306; fig. 2, memory region 202);
providing first work (13:49-55, application program; fig. 5, command stream 500) to be executed by a first processor (3:9-17, central processor of computer system), wherein the first processor executes within a second memory context (fig. 4, memory access operation 410; 3:9-17, modification of memory region);
receiving a first signal (3:34-38, receiving a reference to the modifiable region, unlock command; 13:59-14:12, signal) from the first processor that the first lock can be released;
providing the first signal to a second processor (fig. 1, GPU 0 114-0; 3:38-43, first peripheral co-processor), wherein the second processor executes in the first memory context (3:9-12, master memory region; 13:49-14:12, memory 116-0); and
releasing, by the second processor, the first lock (13:49-55:12, GPU 114-0 updates ref_count; 3:38-43, stop postponing).
As to claims 2, 9 and 16, Diard discloses the method of claim 1, comprising accessing, by the first processor, first data (3:30-38, modification of modifiable region data) associated with the first lock.
As to claims 3, 10 and 17, Diard discloses the method of claim 2,
wherein the first data associated with the first lock is graphics rendering data (fig. 1, rendering module 1200-0), and
wherein the first work is graphics rendering work (fig. 1, scanout module 124-0 to display device 110) based on the graphics rendering data.
As to claims 4-5, 11-12 and 18-19, Diard discloses the method of claim 1, wherein the first signal is received after partial/full (fig. 4, unlock command 412 after full completion of memory access 410; note: after-full includes after-partial) completion of the first work by the first processor.
As to claims 6, 13 and 20, Diard discloses the method of claim 1,
wherein releasing, by the second processor, the first lock is performed responsive to receiving a plurality of signals (13:49-14:12, signal, current_count, ref_count),
wherein the plurality of signals comprises the first signal (13:59-14:12, signal).
As to claims 7, 14, Diard discloses the method of claim 1, comprising:
acquiring a second lock (fig. 4, lock command 406) within a third memory context (fig. 2, another memory region 202);
providing second work (13:49-55, application program; fig. 5, command stream 500) to be executed by a third processor (fig. 1, GPU 114-1), wherein the third processor executes in the second memory context;
receiving a second signal (3:34-38, receiving a reference to the modifiable region, unlock command; 13:59-14:12, signal) from the third processor that the second lock can be released;
providing the second signal to a fourth processor (fig. 1, GPU 0 114-0; 3:38-43, first peripheral co-processor), wherein the fourth processor executes in the third memory context (3:9-12, master memory region; 13:49-14:12, memory 116-0); and
releasing, by the fourth processor, the second lock (13:49-55:12, GPU 114-0 updates ref_count; 3:38-43, stop postponing).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See M.P.E.P 707.05(c).
US 10,108,931 discloses lock-based updating of a document.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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