Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 10, 14 and 18
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 7/1/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 2/17/2025 is empty.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory device and operation method with two different termination impedances for target and non-target memory devices.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12254954. Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare corresponding device, method and system claims sets, we find that same limitations are distributed over the claim ranges.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 13-15 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US 20220050802).
Regarding independent claim 1, Zhao discloses a memory device (Figs. 1A-4), comprising:
an on-die termination (ODT) circuit (Fig. 1A and [0018]-[0021] describes that a single signal line 110A may be illustrated as a representative to demonstrate the ODT technique. The single signal line 110A may be one data signal line of the data bus, DQS, RE, or any signal line that needs ODT. Each storage unit (e.g., 106A.1, 106A.2, 106A.3 and 106A.4) may be a logical unit (LUN) and assigned an identifier, which may be as referred to as a LUN address. A new feature address may be assigned to support ODT as a feature so that the ODT settings may be enabled or modified by a command) configured to provide a configurable termination impedance ([0023] describes that resistance of the termination resistors 112A.1, 112A.2, 112A.3 and 112A.4 may be set by the logic circuit 116A.1 and logic circuit 116A.2 according to the settings in the ODT commands); and
a control logic circuit coupled to the ODT circuit and configured to receive a signal corresponding to a memory operation (Figs. 1A-1B show NAND Controller 102A, 102B and [0017] describes systems and methods for configuring non-target ODT for non-volatile memory device based storage systems),
wherein the ODT circuit is further configured to:
provide a first termination impedance corresponding to the configurable termination impedance in case that the signal indicates the memory device is a target of the memory operation ([0049] describes along with Table 1, the RTT fields of both target and non-target ODT may be set in the four data bytes of one ODT command and the Automatic Enable bit may provide great flexibility and reduce overhead for switching targets. For example, when a selected LUN (e.g., 106A.1) is to be accessed as a target, the NAND device, in which the selected LUN may locate, may enable ODT (e.g., 112A.1) for the selected LUN according to target RTT settings in an ODT command directed to the selected LUN); and
provide a second termination impedance corresponding to the configurable termination impedance in case that the signal indicates the memory device is a non-target of the memory operation ([0049] describes along with Table 1, other LUNs may apply non-target RTT settings according to their respective ODT commands), the second termination impedance being different from the first termination impedance (Table 1, Table 2 and [0035]-[0036]).
Regarding claim 2, Zhao discloses all the elements of claim 1 as above and further an ODT configuration circuit coupled to the ODT circuit and configured to set the ODT circuit to provide the configurable termination impedance (Fig. 1A and [0023] describes logic circuit 116A.1 and logic circuit 116A.2. The logic circuit 116A.1 and 116A.2 may be configured to decode the received ODT commands and turn on ODT according to the configuration in the commands).
Regarding claim 3, Zhao discloses all the elements of claim 1 as above and further a memory, wherein the memory comprises: a first memory area configured to store a target ODT value, and a second memory area configured to store a non-target ODT value, the target ODT value being different from the non-target ODT value (Table 1, Table 2 and [0049]-[0050]).
Regarding claim 4, Zhao discloses all the elements of claim 3 as above and further the memory comprises a volatile memory or a non-volatile memory ([0017]).
Regarding claim 5, Zhao discloses all the elements of claim 3 as above and further the first memory area comprises a first register, and the second memory area comprises a second register (Figs. 1A, 1B and [0021] describes storage unit (e.g., 106A.1, 106A.2, 106A.3 and 106A.4))
Regarding claim 6, Zhao discloses all the elements of claim 3 as above and further the ODT circuit is further configured to provide the first termination impedance based on the target ODT value, or provide the second termination impedance based on the non-target ODT value (Figs. 1A, 1B, Table 1, Table 2 along with [0035]-[0036] and [0049]).
Regarding claim 8, Zhao discloses all the elements of claim 1 as above and further the memory device comprises a volatile memory device or a non-volatile memory device ([0017]).
Regarding claim 9, Zhao discloses all the elements of claim 8 as above and further wherein the non-volatile memory device comprises a flash memory device or a phase change memory device ([0017]).
Regarding independent claim 10, it recites all the limitations of independent claim 1 and henceforth rejected the same way as above.
claim 13, recites the same limitations of claim 5 and henceforth rejected the same way as above.
Regarding independent claim 14, it recites all the limitations of independent claim 1 but drafted in system level with following additional limitations:
Zhao discloses a first memory die and a second memory die (Fig. 1A-1B both shows two non-volatile storage device 104A.1, 104A.2, 104B.1, 104B.2);
a first input/output (I/O) terminal coupled to the first ODT circuit ([0032] that ODT state of the termination resistor may affect the signal transferred on the signal line but does not affect the physical connection from the signal pin of a storage unit to the Input/Output (I/O) signal receiver. For example, if the termination resistor 112A.1 is disabled, the signal line 110A may still be connected to the I/O signal receiver in the storage unit 106A.1);
Rest of claim limitations are same as in claim 1 and henceforth rejected the same way.
Regarding claim 15, Zhao discloses all the elements of claim 14 as above and further the first termination impedance and the second termination impedance are different from each other (Table 1, Table 2 and [0035]-[0036]).
Regarding independent claim 18, it recites all the limitations of independent claim 1 but drafted in method format and henceforth rejected the same way as above.
claims 19-20, recite the same limitations of claims 3 and 6 but drafted in method format and henceforth rejected the same way as above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 11-12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 20220050802) in view of Lee et al. (US 20200219546).
Regarding claim 7, Zhao discloses all the elements of claim 3 as above and through Lee further a multiplexer (Figs 607 show multiplexers), the multiplexer comprising: a first input coupled to the first memory area and configured to receive the target ODT value, a second input coupled to the second memory area and configured to receive the non-target ODT value, a third input coupled to the control logic circuit configured to receive a select signal, and an output coupled to the ODT circuit (Fig. 2 and [0037] describes that mode register 310 may be synchronized with the internal clock signal ICLK to store first and second target termination signals DQ_ODT<1:2>, first and second non-target termination signals NT_ODT<1:2>, the write latency signal WL, the read latency signal RL, a target termination operation signal ODTMR and a non-target termination operation signal NTMR according to the internal chip selection signal ICS and the first to seventh internal command/address signals ICA<1:7> during the mode register write operation. The first and second target termination signals DQ_ODT<1:2>, the first and second non-target termination signals NT_ODT<1:2>, the write latency signal WL, the read latency signal RL, the target termination operation signal ODTMR and the non-target termination operation signal NTMR may be inputted to the mode register 310).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to Zhao in order to provide with systems for performing an on-die termination operation as taught by Lee ([0002]).
Claims 11 and 12 recite similar limitations of claim 7 and henceforth rejected the same way as above.
Claims 16-17 are about positioning two memory dies with respect to two ODT configuration circuits and POSITA would easily derive the conclusion using references Zhao and Lee.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 9/8/2026
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