DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/18/2025. Claims 1-19 are pending in the Application, of which Claim 1 is independent.
Continuity Priority information
The present Application 19055516 filed 02/18/2025 claims foreign priority to TAIWAN, Application No. 114100174, filed 01/02/2025.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/03/2025, 02/18/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, the limitation “receiving a plurality of defect counts of the memory blocks after the access operation” is indefinite, because it fails to define the criterion or condition for determining the defect counts after the access operation. Normally, one performs adjusting a voltage value due to a memory failure.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Any Claims not specifically mentioned above are rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KUROSE et al. (PgPub. US 20200409788) Pub. Date: 2020-12-31.
Regarding independent Claim 1, KUROSE discloses a memory system, comprising:
wherein the memory device comprises a memory array, which performs an access operation according to a reference voltage, Referring to FIGS. 1 and 2, the semiconductor storage device 10 includes, among others, a memory cell array 17. [0055] For example, the sequencer 14 performs a read operation, a write operation, an erasing operation, based on the command CMD stored in the command register 12C and the address information ADD stored in the address register 12B to the “access operation”.
dividing the memory array into a plurality of memory blocks; The memory cell array 17 includes a plurality of blocks BLK0 to BLKn . The memory cell array 17 includes a plurality of bit lines BL0 to BLm (m is an integer larger than or equal to 1), a plurality of word lines WL, a source line CELSRC, and a well line.
adjusting a voltage value of the reference voltage to sequentially perform the access operation on the memory blocks, and receiving a plurality of defect counts of the memory blocks;
As illustrated in FIG. 6, in step S11, the CPU 31 causes the semiconductor storage device 10 to perform read operations “access operation” of a lower page and an upper page. The read voltage based on the correction value table is used in the read operations.
[0099] If the error correction fails in step S13 (step S13, NO), the CPU 31 subsequently performs a retry sequence (step S16) corresponding to “adjusting a voltage value”. In the retry sequence, for example, a shift read in which a predetermined correction is applied to the read voltage, tracking read in which an optimum read voltage is searched by multiple reads, the soft determination decoding process, and the like are performed. In the retry sequence, the operations may be performed a plurality of number of times until the error correction is successful, or a plurality of different types of read may be performed.
judging a defect type of the memory blocks according to the defect counts. [0119] When the memory cell transistor MT stores a plurality of bits of data, the CPU 31 can specify the type of fail bit detected by the error correction process by combining the data before error correction and the data after the error correction.
Regarding Claims 2-6, KUROSE discloses defining the defect type of the memory blocks according to the failed bit count and the failed bit line count. See EXAMPLE,
[0120] “Upper bit before correction/lower bit before correction” .fwdarw.“upper bit after correction/lower bit after correction”: type of corresponding fail bit.
[0121] “11” .fwdarw.“01”: upper tail fail bit TFB of “Er” state.
[0122] “01” .fwdarw.“11”: lower tail fail bit BFB of “A” state.
[0123] “01” .fwdarw.“00”: upper tail fail bit TFB of “A” state.
[0124] “00” .fwdarw.“01”: “lower tail fail bit BFB of “B” state.
[0125] “00” .fwdarw.“10”: upper tail fail bit TFB of “B” state.
[0126] “10” .fwdarw.“00”: lower tail fail bit BFB of “C” state.
Regarding Claims 7-10, KUROSE discloses setting a failed bit count range according to the defect type, and obtaining a voltage value range of the reference voltage corresponding to the failed bit count range. [0127] FIG. 9 illustrates an example of setting of a shift amount of the read voltage in the correction operation of the memory system 1. A fail bit count FBC corresponds to the total fail bit counts between two adjacent states and corresponds to the sum of the lower tail fail bit count BFBC and the upper tail fail bit count TFBC. A fail ratio RAT corresponds to a ratio between the lower tail fail bit count BFBC and the upper tail fail bit count TFBC between two adjacent states and corresponds to, for example, a numerical value obtained by dividing BFBC by TFBC. The shift amount of the read voltage is described by the DAC value. In the present example, a value obtained by multiplying the DAC value by a predetermined voltage value corresponds to the shift amount of the read voltage.
Regarding Claims 11-13, KUROSE discloses recording a plurality of defect addresses of the memory array; As illustrated in FIG. 2. [0052] The status information STS is updated based on an operation state of, for example, the sequencer 14. The status information STS is transferred from the status register 12A to the input/output circuit 11 based on an instruction from the memory controller 30 and is output to the memory controller 30. The address information ADD can be transferred from the input/output circuit 11 to the address register 12B and include, for example, a block address, a page address, a column address, and the like.
Regarding independent Claims 14-17, KUROSE discloses generating a status flag according to the defect type; [0138] Next, the CPU 31 checks whether or not the calculated fail bit count FBC or the fail ratio RAT satisfies a predetermined criterion (step S21). The predetermined criterion is set for each of the fail bit count FBC and the fail ratio RAT. For example, the criterion for the fail bit count FBC is that FBC is less than a predetermined value, and the criterion for the fail ratio RAT is that RAT is in a predetermined range including “1”.
[0139] If FBC or RAT does not satisfy the criterion in step S21 (step S21, NO), the CPU 31 calculates a correction value of the read voltage based on the fail ratio RAT (step S22). The method described with reference to FIG. 9 is applied to the calculation of the correction value.
Regarding Claims 18, 19, KUROSE discloses displaying the failed bit counts and the failed bit line counts of the memory blocks using a second functional test item. [0169] FIG. 14 is an example of stress states of the memory system 1, and illustrates a relationship between the fail bit count FBC and the correction value COL corresponding to each read voltage and the stress state. As illustrated in FIG. 14, the stress states of the memory cell transistor MT include, for example, five types of states (first state to fifth state). [0170] An example of a threshold voltage distribution of the memory cell transistor MT in the first state is illustrated in FIG. 15. In the first state, the fail bit count FBC corresponding to each read voltage is “small”, and the correction value COL for each read voltage is “0”. The threshold voltage distribution in the first state is formed shortly after write and formed when the memory cell transistor MT is not subject to much wear, and corresponds to a state shortly after the write.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 7, 2026
Non-Final Rejection 20260806
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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