DETAILED ACTION
This Non-final action is responsive to the following communications: application filed on 02/18/2025.
Claims 1-20 are pending. Claims 1, 9 and 19 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, undue breadth of the claim may be addressed under different statutory provisions, depending on the reasons for concluding that the claim is too broad. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety.
D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
3. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 02/18/2025. This IDS has been considered.
Specification Objections
4a. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
4b. The disclosure “Background” section does not discuss any meaningful problem to be solved or background information and is objected to. 37 C.F.R. 1.71(b) requires, “The specification must set forth the precise invention for which a patent is solicited, in such manner as to distinguish it from other inventions and from what is old.” Applicant is reminded that helpful guidance, as to preparing an application disclosure, is provided in the MPEP under section 608. Notably, MPEP 608.01(c) provides exemplary use of the heading “Background of the Invention”.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6a. Claims 1, 9, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure.
For claim 1, 9, and 19 omitted elements and omitted essential structural cooperative relationships of elements are:
Description of LP Pump coupled to VPP and VM Pump coupled to VCC (See Fig. 6: 174, 99). See also Fig. 10-12, Fig. 17, Fig. 19, Fig. 21 and associated disclosure of the specific voltage generator circuit. These are critical components of the “voltage generator” and the functionality (of claims 1, 9, and 19 ) and architecture of voltage generator is not understood without description of such components.
An independent claim that omits an essential element can be rejected by a USPTO examiner under 35 U.S.C. 112(b) (indefiniteness/incomplete claiming).
Details/ Triggers of the "Essential Element" Rejection:
• Functional Gap: Omitting these components create an incomplete device or method where the claimed subject matter fails to operate or achieve the stated purpose (e.g., claiming a car but omitting the engine).
• Illustrative vs. Essential: Spec do not describe these features as "preferred," "optional," or "illustrative". See Fig. 6: 174, 99. See also Fig. 10-12, Fig. 17, Fig. 19, Fig. 21 and associated disclosure of the specific voltage generator circuit.
6b. All dependent claims inclusive of claims 1-20 are rejected under this category.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-2, 5, 8, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUZUKI (US 2023/0062829 A1).
Regarding independent claim 1, SUZUKI teaches a memory device (Fig. 2: 10_n “memory chip” for “semiconductor storage device”. See Fig. 5, Fig. 6, Fig. 7) comprising:
a memory cell array including a plurality of memory cells (Fig. 2: 11 memory cell array); and
a voltage generator (Fig. 7: circuitry. See Fig. 2: 17 and associated circuitry) that is supplied with a first external voltage (Fig. 7: VDD “power supply voltage”) and a second external voltage (Fig. 7: VPP “high power supply voltage”) higher than the first external voltage (para [0069]. See also para [0108]) and
generates an operating voltage of the memory cell array (Fig. 7 in context of para [0108]: VREAD),
wherein an operation mode (Fig. 11 read operation 2 for 10_1) of the voltage generator at a time of generating a first voltage value (Fig. 13: VREAD) of the operating voltage includes a first mode (Fig. 11 read operation 2 for 10_1) including a first period (Fig. 11: Assist operation during read operation 2 for 10_1) and a second period after the first period (Fig. 11: Step-up operation during read operation 2 for 10_1), and
the first mode of generating the operating voltage using the first external voltage in the first period (Fig. 12: S1, S2 configuration for 10_1 which generates VREAD from VDD during assist operation) and using the second external voltage in the second period (Fig. 12: S1, S2 configuration for 10_1 which generates VREAD from VPP during step-up operation. See para [0108], para [0129]: VREAD is generated using VDD and VPP. See also para [0155]-para [0157]).
Regarding claim 2, SUZUKI teaches the memory device according to claim 1, wherein in the first mode of the voltage generator, the first external voltage is boosted in the first period, and the second external voltage is stepped down in the second period (Generally VREAD is between VDD and VPP: see in context of Fig. 10, Fig. 22 and thus the described transitions are expected while generating VREAD).
Regarding claim 5, SUZUKI teaches the memory device according to claim 1, wherein the voltage generator includes: a charge pump that boosts the first external voltage; a regulator that adjusts the second external voltage (para [0108], para [0129]);
a first switch circuit provided between the charge pump and the regulator Fig. 7: combination of S1, S2); and
a second switch circuit provided between a voltage node to which the second external voltage is supplied and the regulator (Fig. 7: S2).
Regarding claim 8, SUZUKI teaches the memory device according to claim 1, wherein the voltage generator generates a voltage to be applied to a non-selected word line in the memory cell array in a read operation or a write operation (para [0146]: “…voltage VREAD is supplied to a non-selected word line…”).
Regarding independent claim 19, SUZUKI teaches a memory device (Fig. 2: 10_n “memory chip” for “semiconductor storage device”. See Fig. 5, Fig. 6, Fig. 7) comprising:
a memory cell array including a plurality of memory cells (Fig. 2: 11 memory cell array); and
a voltage generator (Fig. 7: circuitry. See Fig. 2: 17 and associated circuitry) including a first node (Fig. 7: VDD input node) to which a first external voltage is supplied (Fig. 7: VDD “power supply voltage”),
a second node (Fig. 7: TVPP) to which a second external voltage (Fig. 7: VPP “high power supply voltage”. See Fig. 7: VPP is supplied to TVPP terminal) higher than the first external voltage is supplied (para [0069]. See also para [0108]), and
a third node (Fig. 7: output of RE1 node) that outputs an operating voltage of the memory cell array (Fig. 7: VREAD),
the voltage generator generating the operating voltage using at least one of the first and second external voltages (See para [0108], para [0129]: VREAD is generated using VDD and VPP. See also para [0155]-para [0157]),
wherein the voltage generator includes a plurality of pump circuits (para [0130], Fig. 7: diode-capacitor stages within CP0) that boosts the first external voltage (Fig. 7: VDD) and is connected in series between the first node (Fig. 7: VDD input node) and the third node (Fig. 7: output of RE1 node), and
at a time (functional feature shown in Fig. 13) of generating the operating voltage using the second external voltage (Fig. 13: during step-up operation for 10_1 using VPP when S1, S2 are closed), the voltage generator charges a first pump circuit (Fig. 7, Fig. 13: CP0-CP3 are supplied with VDD, CLK, CS) connected to the third node (Fig. 13: RE1 node) among the pump circuits (Fig. 13: considering pump circuits in 10_1, 10_0).
Regarding claim 20, SUZUKI teaches the memory device according to claim 19, wherein the voltage generator (Fig. 7 circuitry) further includes a first regulator (Fig. 7: RD, RE1 combined) that adjusts the second external voltage (para [0108], para [0069]), and
a charge transfer path of the first pump circuit (Fig. 7: D1 input to D3 output path) is charged by a voltage output from the first regulator (Fig. 7: feedback/ RD output transmits charge on the pump path. RE1 output and feedback/ RD output are correlated).
10. Claims 9-11, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KATAOKA et al. (US 2024/0071478 A1).
Regarding independent claim 9, KATAOKA teaches a memory device (Fig. 4: MD memory die employing Fig. 6 circuitry) comprising:
a memory cell array including a plurality of memory cells (Fig. 4: MCA); and
a voltage generator (Fig. 6 circuitry) including a first node (Fig. 6: vg1 supply input. See Fig. 7, Fig. 8 in relation to Fig. 6) to which a first external voltage is supplied (Fig. 7, Fig. 8: Vcc),
a second node (Fig. 6: P) to which a second external voltage higher than the first external voltage is supplied (Fig. 6: Vpp. See Fig. 4: supply pin hierarchy shows Vpp level is higher than Vcc level), and
a third node (Fig. 6: CG node) that outputs an operating voltage of the memory cell array (para [0092]),
the voltage generator generating the operating voltage using at least one of the first and second external voltages (Fig. 6-Fig. 8 in context of para [0081]-para [0083]),
wherein the voltage generator includes a plurality of pump circuits (Fig. 8 circuitry with pump stages employed in vg1. Para [0085]) that is connected in series between the first node (Fig. 6: vg1 supply input. See Fig. 8: Vcc input) and the third node (Fig. 6: CG. See Fig. 8: Vout) and that boosts the first external voltage (para [0085]: circuit function of Fig. 8), and
a first pump circuit (Fig. 8 circuitry with vg1) connected to the third node (see Fig. 6: CG in relation to Fig. 8: Vout) among the pump circuits includes:
one or more charge transfer switches (Fig. 3: 32a3 capacitors) connected between the first node (Fig. 8: Vcc node) and the third node (Fig. 8: Vout node); and
one or more diode-connected transistors (Fig. 8: 32a2a, 32a2b….diode connected transistors) having diode-connection (Fig. 8) and connected in parallel to a charge transfer path of the charge transfer switch (see Fig. 8: 32a3, 32a2a parallel coupling).
Regarding claim 10, KATAOKA teaches the memory device according to claim 9, wherein the voltage generator includes: a second pump circuit (Fig. 8 circuitry with vg2) provided between (provided between interpreted in association with coupling) the first node and the first pump circuit (Fig. 8: vg2 is coupled to vg1 output and input and thus the limitation is satisfied) ; and
a first switch (Fig. 6: SW1) provided between an input node of the first pump circuit (Fig. 6: input of vg1) and an output node of the second pump circuit (Fig. 6: output of vg2).
Regarding claim 11, KATAOKA teaches the memory device according to claim 9, wherein when the first pump circuit is stopped, the charge transfer path of the charge transfer switch is charged via the diode-connected transistor (para [0085], Fig. 8: 3212a, 32a2b coupling to capacitor 32a3 and level shifter 32a5b would satisfy this functional limitation for propagating FB).
Regarding claim 13, KATAOKA teaches the memory device according to claim 9, wherein the voltage generator further includes: a second pump circuit (Fig. 8 circuitry with vg2) provided between the first node and the first pump circuit (see claim 10);
a first switch provided between an input node of the first pump circuit and an output node of the second pump circuit (see claim 10);
a second regulator (Fig. 6, Fig. 7: 32c with vg2) provided between an output node of the second pump circuit (Fig. 7: Lvg2) and the third node (Fig. 6: CG) and
a second switch (Fig. 6: TDRV1) connected between an output node of the second regulator (Fig. 7: FB in vg2. See Fig. 6) and the input node of the first pump circuit (Fig. 6: input to vg1).
Prior Art Not Relied Upon but Pertinent
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: NAKANO (US 2022/0301630 A1): Fig. 8-Fig. 13 applicable for all claims. Cazzaniga (US 2010/0074034 A1) is applicable for all claims. Cazzaniga teaches a voltage generator (Fig. 1: 100 “voltage regulator” and associated circuitry. See also Fig. 4 and Fig. 5) comprising: at least one driving circuit (Fig. 1: 102. See Fig. 5: 102) connected to a plurality of word lines of a memory device (e.g. terminal B of Fig. 5: 200 “memory cell”. para [0041]: “word lines” in a cross-point nonvolatile memory array), the at least one driving circuit (Fig. 5: 102) configured to provide a current (Fig. 5: I_Load) for increasing voltages of the plurality of word lines (Fig. 5: Vout) based on a reference voltage (Fig. 5 in context of para [0052]: input reference voltage VBG which coupled with feedback voltage from output Vout); a current sensing circuit (means for detecting e.g. Fig. 7D: ILoad) configured to detect a magnitude of a charge current input (e.g. Fig. 7D: ILoad) to the at least one driving circuit , a peak detect circuit (means for detecting e.g. Fig. 7D: Imax or Fig. 9: ILoadmax) configured to compare the detected magnitude of the charge current with a peak current value (Fig. 7D: ILoad vs. Imax is detected and taken as circuitry functionality)
BAEK et al. (US 2020/0111513 A1): Fig. 1-Fig. 7 disclosure applicable for all claims 2, 6-9, 15-18. BAEK teaches memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.
It is suggested that applicant consider all prior arts made of record .
Allowable Subject Matter
Claims 3-4, 6-7, 12, and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In addition, associated 112b rejections (see section 6a, 6b) of all claims must be over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/
Primary Examiner, Art Unit 2825
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