DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 02/18/2025 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 02/18/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-9 & 13-14 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Jackson et al (US5201029).
Regrading claim 1, Jackson discloses a memory device(FIG 2), comprising: a plurality of first memory cells arranged over a plurality of first columns and a plurality of rows(memory array comprising cells 29s arrange over columns and rows), wherein the plurality of first memory cells are commonly coupled to a first bit line(29A-29D cells common coupled to e.g., 32); and a plurality of first logic gates(41-43), wherein each of the plurality of first logic gates has a first input, a second input, and an output(41-43 each having first input c , second input d and output 38), the output of the first logic gate connected to a corresponding one of the plurality of first memory cells(41 output 38 is connected to memory cell 29A and so on).
Regrading claim 2, Jackson discloses Further comprising: a plurality of word lines disposed along the plurality of rows(FIG 2; rows), respectively; and a plurality of first bit select lines disposed along the plurality of first columns, respectively (FIG 2; 30 and 34).
Regarding claim 7, Jackson discloses wherein the first bit line includes multiple portions in parallel with the rows, respectively, and one portion extending in parallel with the first columns (FIG 2; 30 32 33 34 and so on).
Regarding claim 8, Jackson discloses wherein each of the first logic gates includes an AND logic gate (FIG 2-3; AND gate).
Regarding claim 9, Jackson discloses further comprising: a plurality of second memory cells arranged over a plurality of second columns and the plurality of rows(FIG 2; 29E-29H), wherein the plurality of second memory cells are commonly coupled to a second bit line(33); a plurality of second logic gates, wherein each of the plurality of second logic gates has a first input, a second input, and an output(42 c d), the output of the second logic gate connected to a corresponding one of the plurality of second memory cells(42 output 39 connected to 29E).
Regarding claim 13, Jackson discloses a memory device, comprising: a plurality of first memory cells arranged over a plurality of first columns and a plurality of rows(FIG 2; 29A-29L arranged overed columns and rows), wherein the plurality of first memory cells are commonly coupled to a first bit line(29A-29D cells common coupled to e.g., 32); a plurality of first logic gates, wherein each of the plurality of first logic gates has a first input, a second input, and an output connected to a corresponding one of the plurality of first memory cells(FIG 2; 41 having c and d inputs and an output of 38 connected to 29A);
a plurality of second memory cells arranged over a plurality of second columns and the plurality of rows(29E-29H), wherein the plurality of second memory cells are commonly coupled to a second bit line(33); and a plurality of second logic gates, wherein each of the plurality of second logic gates has a first input, a second input, and an output connected to a corresponding one of the plurality of second memory cells (42 having c and d and an output of 39 connected to 29E).
Regarding claim 14, Jackson discloses further comprising: a plurality of word lines disposed along the plurality of rows (FIG 2; rows), respectively; a plurality of first bit select lines disposed along the plurality of first columns, respectively; and a plurality of second bit select lines disposed along the plurality of second columns, respectively (FIG 2; 30 and 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 & 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jackson et al in view of Katakura et al (US20220068414).
Regarding claim 5, Jackson discloses wherein each of the first memory cells (FIG 1; 29).
However, Jackson does not disclose includes a transistor and a fuse resistor connected to each other in series.
However, in the field of endeavor, Katakura discloses includes a transistor and a fuse resistor connected to each other in series (FIG 12; 27 comprising transistor LVND1 in series with fuse resistor R2-1).
Jackson and Katakura are analogous art because they are all directed to a semiconductor device with conductive state device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Jackson to include Katakura because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Katakura in the teachings of Jackson for the benefits of having better conductive state of the semiconductor device. [0005 Katakura].
Regarding claim 6, The combinations of Jackson in view of Katakura disclose wherein the fuse resistor has a first end coupled to the first bit line and a second end connected to a drain/source terminal of the transistor (Katakura FIG 12; R2-1 first end coupled to the bit line and a second end connected to d/s of LVND1).
Regarding claim 18, Jackson discloses a memory device, comprising: a plurality of memory cells arranged over a plurality of columns and a plurality of rows, wherein the plurality of memory cells(FIG 2; 29A-29L arranged in rows and columns), and a plurality of logic gates(41-42), wherein each of the plurality of logic gates has a first input, a second input, and an output, the output of the logic gate connected to of a corresponding one of the plurality of memory cells (41 having c d inputs and an output of 38 connected to 29A).
However, Jackson does not disclose each including a transistor and a fuse resistor connected to each other in series, are commonly coupled to a bit line; a gate terminal of the transistor.
In the same field of endeavor, Katakura discloses each including a transistor and a fuse resistor connected to each other in series (FIG 12; 27 comprising transistor LVND1 in series with fuse resistor R2-1), are commonly coupled to a bit line FIG 12; R2-1 first end coupled to the bit line and a second end connected to d/s of LVND1); a gate terminal of the transistor(LVND1 having a terminal gate).
Jackson and Katakura are analogous art because they are all directed to a semiconductor device with conductive state device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Jackson to include Katakura because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Katakura in the teachings of Jackson for the benefits of having better conductive state of the semiconductor device. [0005 Katakura].
Regarding claim 19, the combinations of Jackson in view of Katakura disclose wherein the bit line includes multiple portions in parallel with the rows, respectively, and one portion extending in parallel with the plurality of columns (Jackson FIG 2; 30 32 33 34 and so on).
Regarding claim 20, Je combinations of Jackson in view of Katakura disclose wherein each of the logic gates includes an AND logic gate (FIG 2-3; AND gate).
Allowable Subject Matter
Claims 3-4, 10-12, 15-17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Akiyoshi et al (US20070103956 FIG 2; [0042] discloses SA, a two input NAND gate whose inputs are connected to the bitlines of array).
Nii et al (US20060262628 FIG 8; discloses the first input and second input of NG1 connected to BL and /BL).
Walther et al (US7085184 FIG 2; discloses BL connected to the input of logic 40).
Lin et al (US10650882 FIG 2A; discloses BLB [0] connected to input of NOR1 and MRC connected a second input of NOR1).
Ramaraju et al (US9224439 FIG 2; discloses output of logic 224 coupled to output of 226 coupled to the WL0).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/ Primary Examiner, Art Unit 2827
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