Prosecution Insights
Last updated: October 26, 2026
Application No. 19/056,300

METHOD OF FORMING PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Feb 18, 2025
Priority
Mar 07, 2024 — RE 10-2024-0032841
Examiner
DEO, DUY VU NGUYEN
Art Unit
1713
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
870 granted / 1055 resolved
+17.5% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
33 currently pending
Career history
1085
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
13.8%
-26.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1055 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7, 8, 10, 11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Park et al. (US 8,551,689B2) (referred as Park ‘689). With respect to claim 1, Park ‘689 describes a method for forming a pattern comprising: providing a lower surface 1000 having at least one layer to be etched on a substrate and an anti-reflective film 500 (or 500a) or under layer on the layer to be etched (col. 5, lines 50-65; col. 9, lines 60-62; col. 10, lines 4-17; fig.2) PNG media_image1.png 200 400 media_image1.png Greyscale ; forming a first resist pattern 110a on the anti-reflective film 500a PNG media_image2.png 200 400 media_image2.png Greyscale (fig. 7A; col. 14, line 22-col. 15, line 15); forming a second resist layer 300 covering a side wall and a top surface of the first resist pattern and extending on a top surface of the under layer PNG media_image3.png 200 400 media_image3.png Greyscale (fig. 8A; col. 15, lines 43-50); forming a second resist pattern 310 covering the side wall of the first resist pattern by removing a portion of the second resist layer 300 on top of the under layer to form a resist structure comprising the first resist pattern 100a and the resist pattern 310 PNG media_image4.png 200 400 media_image4.png Greyscale (fig. 11A; col. 17, lines 1-18); etching the anti-reflective layer 500a and the lower surface 1000 to obtain a pattern 1000p using the resist structure to obtain a pattern 500p and 1000p PNG media_image5.png 200 400 media_image5.png Greyscale (col. 17, line 18-33; fig. 12A). With respect to claim 7, the method further includes forming a third photoresist on and covering the second photoresist and processing the third photoresist in the same way as that of the second photoresist including removing a portion of the third photoresist to form a photoresist structure comprising the third photoresist (col. 19, line 59-col. 20, line 3). With respect to claim 8, the etching target layer including the anti-reflective 500 includes organic and inorganic film such as carbon, SiN, or SiNxOy (col. 10, lines 25-28), which is expected to have a concentration of tin of 1E11/cm3 or less. With respect to claim 10, the method describes above further shows in fig. 7A, the first resist pattern 110a overlaps a first portion and expose or does not overlap a second portion of the etching target layer 500a. The second resist pattern 310 in fig. 11a above is formed by a developing process on the second resist layer (col. 17, lines 5-15). With respect to claim 11, the first and second resist is substantially the same (col. 15, lines 52-55). Since the steps forming the first and second resist pattern are the same as that of the claimed invention that provide the second resist pattern on the sidewalls of the first resist pattern, the second resist pattern would also be less dense than the first resist pattern. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Lu (US 2024/0134275A1). With respect to claims 2 and 9, Park doesn’t teach that the first and second photoresist containing tin oxide and are formed by EUV. He teaches the first and second photoresist may be the same and using commonly methods using UV and DUV (col. 6, lines 17-25; col. 15, lines 52-57). However, using photoresist having tin oxide for EUV or DUV is practiced by one skilled in the art as shown here by Lu (para 64, 68). Therefore, it would have been obvious for one skilled in the art before the effective filing date of the invention to use known photoresist techniques such as one having tin oxide and EUV process in order to provide photoresist mask for the etching with expected results. Claim(s) 16, 17, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 8,551,689B2) (referred as Park ‘689), and further in view of Lee et al. (KR 20230094004 A). With respect to claims 16, 17, Park ‘689 teaches a method for forming a pattern, please see rejection of claim 1 above. Unlike claimed invention, he doesn’t teach the photoresist structure and the antireflective layer are formed on a device isolation layer, direct contacts, bit lines, conductive plugs, a landing layer, a mask pattern, an under layer and a under pattern, and etching the landing layer to form landing pads using the photoresist structure and the mask pattern. However, etching landing layer to form landing pads using the photoresist structure and the mask pattern on a structure that includes a device isolation layer, direct contacts, bit lines, conductive plugs, a landing layer, a mask pattern, an under layer and a under pattern is known in the art as shown here by Lee. He teaches providing a device isolation layers including insulating capping pattern 136, insulating layer 158, insulating spacer 142 (page 12); direct contacts DC, multifunction conductive plugs on bit lines; landing layer LP (pages 3, 4); hardmask HM structure including under layer and under pattern M1-M4 and a photoresist pattern MP2 (fig. 4L; page 12), wherein the photoresist pattern and the hardmask pattern are used for etching under layer including the landing layer LP (fig. 4n) PNG media_image6.png 586 306 media_image6.png Greyscale PNG media_image7.png 478 352 media_image7.png Greyscale , PNG media_image8.png 400 298 media_image8.png Greyscale . It would have been obvious for one skilled in the art before the effective filing date of the invention to provide a structure under the photoresist and hardmask for etching, such structure including a landing layer to be etched under a hardmask in light of Lee because Lee teaches that such structure would form an integrated circuit device including a capacitor (page 1) with expected results. With respect to claims 19 and 20, the landing pads LP include metal film 156 made of W (page 7), which is expected to have tin concentration of 1E11/cm3 or less. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park ‘689 and Lee as applied to claim 16 above, and further in view of Park et al. (US 2022/0037251A1) (referred as Park ‘251). With respect to claim 18, Park ‘689 doesn’t teach a pitch of the landing pads is in a range of 26 nm to 39 nm. However, this range for a landing pads is known to one skilled in the art as shown here by Park ‘251, who teaches the landing pad pattern has a pitch of less than 40 nm (claim 14). It would have been obvious for one skilled in the art before the effective filing date of the invention to use a pitch in the range of 26nm to 39 nm because it has been successfully used to make a semiconductor device with expected results. Allowable Subject Matter Claims 3, 4, 5, 6, 12, 13, 14, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 is allowed over the applied prior art because Park ‘689 doesn’t teach a width of the top surface of the first resist pattern is greater than a width of a middle portion of the first resist pattern, wherein a width of a lower surface of the first resist pattern is greater than the width of the middle portion of the first resist pattern, and wherein the second resist pattern covers a side wall of the middle portion of the first resist pattern. Claims 4 and its dependent claim 5 and 6 are allowed over the applied prior art because neither Park ‘689 nor Lu teach an exposure process is not performed on the second photoresist layer in combination with other limitations of claims 1 and 4. Claim 12 is allowed over the applied prior art because Park ‘689 doesn’t teach a difference between a maximum width and a minimum width of the second resist pattern is less than a difference between a maximum width and a minimum width of the first resist pattern. Claims 13 and its dependent claims 14, 15 are allowed over the applied prior art because neither Park ‘689 nor Lu teach performing a first dry developing process on the first resist layer, performing a bake process on the second resist layer, wherein the developing process on the second resist layer comprises a second dry developing process, and wherein an exposure process is not performed on the second resist layer in combination with other limitations in claim 13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY VU NGUYEN DEO whose telephone number is (571)272-1462. The examiner can normally be reached 9-5 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-272-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY VU N DEO/Primary Examiner, Art Unit 1713 10/8/2026
Read full office action

Prosecution Timeline

Feb 18, 2025
Application Filed
Oct 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
90%
With Interview (+7.3%)
2y 4m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1055 resolved cases by this examiner. Grant probability derived from career allowance rate.

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