Listed by the USPTO as DEO, DUY VU NGUYEN
Tech Center 2800 • Art Units: 1713 1716 1765 1792 1794 2817
This examiner grants 82% of resolved cases
DEO, DUY VU NGUYEN is assigned to Tech Center 2800 and Art Unit 1713. The record contains 1055 resolved cases, an 82.5% allowance rate, and a median of 873 days to allowance. The 7.3% interview lift is positive but modest relative to the overall allowance rate, so interviews appear to be a supporting rather than defining feature of this profile.
The listed companies are Tokyo Electron Limited, RESONAC Corporation, and Samsung Electronics Co., Ltd. The listed firms are BIRCH STEWART KOLASCH & BIRCH, LLP, FITCH, EVEN, TABIN & FLANNERY, LLP, and IPUSA, P.L.L.C. The data supports careful claim presentation and docket planning, with a substantial allowance history but a median timeline that still requires attention.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18808281 | COMPOSITION FOR MANUFACTURING SEMICONDUCTOR, METHOD FOR TREATING OBJECT TO BE TREATED, AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT | Final Rejection | FUJIFILM Corporation |
| 19056300 | METHOD OF FORMING PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18947090 | ETCHING COMPOSITIONS, METHODS OF TREATING SUBSTRATES USING THE SAME, AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES USING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18651935 | METHOD, SYSTEM AND APPARATUS FOR SURFACE MODIFICATION | Final Rejection | ASM IP Holding B.V. |
| 18839177 | SELECTIVE PRECISION ETCHING OF SEMICONDUCTOR MATERIALS | Non-Final OA | Lam Research Corporation |
| 18771442 | EFFICIENT CLEANING AND ETCHING OF HIGH ASPECT RATIO STRUCTURES | Non-Final OA | LAM RESEARCH CORPORATION |
| 18826539 | ETCHING METHODS AND PATTERNED SUBSTRATES MADE USING SAID METHODS | Non-Final OA | Ohio State Innovation Foundation |
| 18951442 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING SYSTEM | Non-Final OA | Tokyo Electron Limited |
| 18816114 | SUBSTRATE-PROCESSING METHOD AND SUBSTRATE-PROCESSING DEVICE | Non-Final OA | Tokyo Electron Limited |
| 18626693 | SUBSTRATE-PROCESSING METHOD AND SUBSTRATE-PROCESSING APPARATUS | Non-Final OA | Tokyo Electron Limited |
| 19099595 | PLASMA PROCESSING METHOD | Non-Final OA | Hitachi High-Tech Corporation |
| 18866369 | METHOD FOR PRODUCING AQUEOUS SOLUTION OF PURIFIED AMINOSILANOL COMPOUND AND AMINOSILOXANE COMPOUND, AND COMPOSITION FOR ETCHING | Non-Final OA | SHIN-ETSU CHEMICAL CO., LTD. |
| 18911657 | METHOD FOR RECYCLING RARE EARTH SINTERED MAGNET | Non-Final OA | SHIN-ETSU CHEMICAL CO., LTD. |
| 19064895 | SEMICONDUCTOR STRUCTURE WITH REDUCED GATE CONTACT RESISTANCE AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18626386 | SEMICONDUCTOR DEVICE FABRICATION METHODS AND DEVICES FOR FORMING THE SAME | Final Rejection | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18615579 | SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION | Final Rejection | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18867945 | ETCHING METHOD | Non-Final OA | Resonac Corporation |
| 18857335 | ABRASIVE GRAIN, SELECTION METHOD THEREFOR, POLISHING AGENT, MULTI-LIQUID POLISHING AGENT, POLISHING METHOD, COMPONENT MANUFACTURING METHOD, AND SEMICONDUCTOR COMPONENT MANUFACTURING METHOD | Non-Final OA | Resonac Corporation |
| 18879868 | SUBSTRATE PROCESSING METHOD | Non-Final OA | SCREEN Holdings Co., Ltd. |
| 18574352 | METHOD FOR MANUFACTURING AN EMITTER FOR ELECTROSPRAY GENERATORS | Final Rejection | INSTITUCIÓ CATALANA DE RECERCA I ESTUDIS AVANÇATS |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy82.5% of resolved applications examined by Duy Vu Nguyen Deo were allowed (1,055 resolved cases), compared with 62.4% across Art Unit 1713 over the last five years.
This examiner's interview lift is +7.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Duy Vu Nguyen Deo took 873 days on average from filing to allowance.
Duy Vu Nguyen Deo examines applications in Art Unit 1713 in Tech Center 2800 (Semiconductors, Circuits & Optics).
