DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) [ 1-5, 7 ] are rejected under 35 U.S.C. 103 as being unpatentable over [Patange (US Pub No. 20190080111), hereinafter "Patange", in view of Bartling et al. (US 8854079), hereinafter "Bartling" ].
As per claim 1, Patange significantly teaches an integrated circuit, comprising: a first memory cell array configured to store a first set of data (retrieving, by the memory controller, the payload data from the memory area [Patange PP 0009]);
an error correction code (ECC) decoder coupled to the first set of inverters and the first memory cell array, and configured to at least detect or correct an error in at least a second set of data or the second set of check bits thereby generating at least a set of output data and a been- attacked signal, the second set of data corresponds to the first set of data stored in the first memory cell array, and the been-attacked signal indicating a reset attack by a user (data check module 19 implementing a first check mechanism and a second check mechanism [Patange PP 0046], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset [Patange PP 0052], to check the payload data using the second check data according to a first check mechanism (comprised in the data check module 19 ), to detect failing [Patange PP 0047]).
Patange does not explicitly teach “a second memory cell array configured to store a first inverted set of check bits; a first set of inverters coupled to the second memory cell array and being configured to generate a second set of check bits in response to a third set of check bits, and the third set of check bits being inverted from the second set of check bits, and the third set of check bits corresponds to the first inverted set of check bits stored in the second memory cell array;”
However, Bartling, in an analogous art, teaches a second memory cell array configured to store a first inverted set of check bits (Before storing the parity bit, it is inverted [Bartling PP 0024], NVL array 110 is implemented with an array 1040 of eight rows and thirty-two columns of bitcells [Bartling PP 0074], thirty-one data columns and one parity column [Bartling PP 0094]);
a first set of inverters coupled to the second memory cell array and being configured to generate a second set of check bits in response to a third set of check bits, and the third set of check bits being inverted from the second set of check bits, and the third set of check bits corresponds to the first inverted set of check bits stored in the second memory cell array (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 2, Patange does not explicitly teach “wherein the ECC decoder comprises: a syndrome generator coupled to the first set of inverters and the first memory cell array, and configured to generate a syndrome vector in response to the second set of data and the second set of check bits.”
However, Bartling, in an analogous art, teaches wherein the ECC decoder comprises: a syndrome generator coupled to the first set of inverters and the first memory cell array, and configured to generate a syndrome vector in response to the second set of data and the second set of check bits (Each IO driver section … may contain an XOR gate 1160 [Bartling PP 0090], The output of XOR gate 1160 that is in bit column 30 is the overall parity value for the row of data that was read from bit columns 0 : 30 and is used to compare to a parity value read from bit column 31 by parity error detector XNOR gate 1370 . If the overall parity value determined from the read data does not match the parity bit read from column 31 , then a parity error is indicated [Bartling PP 0091]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 3, Patange significantly teaches wherein the ECC decoder further comprises: an error detection/correction logic circuit coupled to the syndrome generator and the first memory cell array, and being configured to generate the set of output data in response to at least the second set of data and the syndrome vector (data check module 19 [Patange PP 0047], the first check mechanism and the second check mechanism both comprise a same hash function and/or checksum algorithm [Patange PP 0026]).
As per claim 4, Patange significantly teaches wherein the ECC decoder comprises: a first logic circuit configured to determine if the integrated circuit has been attacked by the user by detecting an invalid codeword, the invalid codeword including the second set of check bits and the second set of data (to check the payload data using the second check data according to a first check mechanism (comprised in the data check module 19 ), to detect failing [Patange PP 0047], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset. [Patange PP 0052]).
As per claim 5, Patange does not explicitly teach “wherein the first logic circuit comprises: a second set of inverters coupled to the first set of inverters and being configured to generate a fourth set of check bits in response to the second set of check bits, the fourth set of check bits being inverted from the second set of check bits.”
However, Bartling, in an analogous art, teaches wherein the first logic circuit comprises: a second set of inverters coupled to the first set of inverters and being configured to generate a fourth set of check bits in response to the second set of check bits, the fourth set of check bits being inverted from the second set of check bits (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 7, Patange does not explicitly teach “wherein the first memory cell array includes: magnetoresistive random-access memory (MRAM); or phase-change RAM (PRAM).”
However, Bartling, in an analogous art, teaches wherein the first memory cell array includes: magnetoresistive random-access memory (MRAM); or phase-change RAM (PRAM) (other embodiments of the invention will be apparent to persons skilled in the art [Bartling PP 0118] obvious alternative memory types).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
Claim(s) [ 6, 8-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Patange, in view of Bartling, in further view of Kaabouch et al. (US US 7774587), hereinafter "Kaabouch"].
As per claim 6, Patange in view of Bartling do not explicitly teach “wherein the first logic circuit further comprises: a first NOR logic circuit coupled to the first memory cell array and the second set of inverters, and configured to generate the been-attacked signal in response to the fourth set of check bits and the second set of data.”
However, Kaabouch, in analogous art, teaches wherein the first logic circuit further comprises: a first NOR logic circuit coupled to the first memory cell array and the second set of inverters, and configured to generate the been-attacked signal in response to the fourth set of check bits and the second set of data (comparator represented by the NAND gate 154 [Kaabouch PP 0021] a logic comparator that generates an attack signal; using NOR instead of NAND is obvious).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 8, Patange significantly teaches an integrated circuit, comprising: an error correction code (ECC) encoder configured to generate a first set of check bits in response to a first set of data (data check module 19 implementing a first check mechanism and a second check mechanism [Patange PP 0047], the first check mechanism and the second check mechanism both comprise a same hash function and/or checksum algorithm [Patange PP 0026]);
an ECC decoder coupled to the first set of inverters and the second memory cell array, and configured to at least detect or correct an error in at least the second set of data or a second set of check bits thereby generating at least a set of output data and a been-attacked signal, the second set of check bits corresponds to the first set of check bits stored in the second memory cell array, and the been-attacked signal indicating a reset attack by a user (data check module 19 implementing a first check mechanism and a second check mechanism [Patange PP 0046], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset. [Patange PP 0052], to check the payload data using the second check data according to a first check mechanism (comprised in the data check module 19 ), to detect failing [Patange PP 0047]).
Patange does not explicitly teach “a first memory cell array configured to store a first inverted set of data inverted from the first set of data; a second memory cell array coupled to the ECC encoder, and configured to store the first set of check bits; a first set of inverters coupled to the first memory cell array and being configured to generate a second set of data in response to a third set of data, the third set of data being inverted from the second set of data, and the third set of data corresponds to the first inverted set of data stored in the first memory cell array;”
However, Bartling, in an analogous art, teaches a first memory cell array configured to store a first inverted set of data inverted from the first set of data (Before storing the parity bit, it is inverted [Bartling PP 0024] teaches storing inverted bits; inverting data instead of parity is an obvious equivalent);
a first set of inverters coupled to the first memory cell array and being configured to generate a second set of data in response to a third set of data, the third set of data being inverted from the second set of data, and the third set of data corresponds to the first inverted set of data stored in the first memory cell array (the parity bit to be read, inverted, and written back. [Bartling PP 0095] the operation of inverting on read is directly taught; applying it to data is obvious);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
Patange in view of Bartling do not explicitly teach “a second memory cell array coupled to the ECC encoder, and configured to store the first set of check bits”
However, Kaabouch, in analogous art, teaches a second memory cell array coupled to the ECC encoder, and configured to store the first set of check bits (The checker memory 130 is a dedicated memory separate from the memory 100 storing data to be protected. [Kaabouch PP 0021])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 9, Patange does not explicitly teach “wherein the ECC decoder comprises: a syndrome generator coupled to the first set of inverters and the second memory cell array, and configured to generate a syndrome vector in response to the second set of data and the second set of check bits.”
However, Bartling, in an analogous art, teaches wherein the ECC decoder comprises: a syndrome generator coupled to the first set of inverters and the second memory cell array, and configured to generate a syndrome vector in response to the second set of data and the second set of check bits (Each IO driver section … may contain an XOR gate 1160 [Bartling PP 0090], The output of XOR gate 1160 that is in bit column 30 is the overall parity value for the row of data that was read from bit columns 0 : 30 and is used to compare to a parity value read from bit column 31 by parity error detector XNOR gate 1370 . If the overall parity value determined from the read data does not match the parity bit read from column 31 , then a parity error is indicated. [Bartling PP 0091]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 10, Patange significantly teaches wherein the ECC decoder further comprises: an error detection/correction logic circuit coupled to the syndrome generator and the first set of inverters, and configured to generate the set of output data in response to at least the second set of data and the syndrome vector (data check module 19 implementing a first check mechanism and a second check mechanism [Patange PP 0046], the first check mechanism and the second check mechanism both comprise a same hash function and/or checksum algorithm [Patange PP 0026]).
As per claim 11, Patange in view of Bartling do not explicitly teach “wherein the error detection/correction logic circuit comprises: an OR logic gate coupled to the syndrome generator and configured to generate an error detected signal in response to the syndrome vector, the error detected signal indicating whether the error in the second set of check bits and the second set of data is detected.”
However, Kaabouch, in analogous art, teaches wherein the error detection/correction logic circuit comprises: an OR logic gate coupled to the syndrome generator and configured to generate an error detected signal in response to the syndrome vector, the error detected signal indicating whether the error in the second set of check bits and the second set of data is detected (comparator represented by the NAND gate 154 [Kaabouch PP 0021] routine logic substitution).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 12, Patange does not explicitly teach “wherein the error detection/correction logic circuit further comprises: a syndrome decoder coupled to the syndrome generator, and configured to generate an error signal in response to the syndrome vector, the error signal identifying at least a location of the error in the second set of check bits and the second set of data; and a set of exclusive OR (XOR) gates coupled to the syndrome decoder, the second memory cell array and the first set of inverters, and being configured to generate the set of output data in response to the error signal, the second set of data and the second set of check bits.”
However, Bartling, in an analogous art, teaches wherein the error detection/correction logic circuit further comprises: a syndrome decoder coupled to the syndrome generator, and configured to generate an error signal in response to the syndrome vector, the error signal identifying at least a location of the error in the second set of check bits and the second set of data (The output of XOR gate 1160 that is in bit column 30 is the overall parity value for the row of data that was read from bit columns 0 : 30 and is used to compare to a parity value read from bit column 31 by parity error detector XNOR gate 1370 . If the overall parity value determined from the read data does not match the parity bit read from column 31 , then a parity error is indicated. [Bartling PP 0091]); and
a set of exclusive OR (XOR) gates coupled to the syndrome decoder, the second memory cell array and the first set of inverters, and being configured to generate the set of output data in response to the error signal, the second set of data and the second set of check bits (Each IO driver section … may contain an XOR gate 1160 [Bartling PP 0090]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 13, Patange in view of Bartling do not explicitly teach “wherein the error detection/correction logic circuit further comprises: a NOR logic gate coupled to the syndrome decoder, and configured to generate a NOR output signal in response to the error signal; and an AND logic gate coupled to the OR logic gate and the NOR logic gate, and configured to generate an uncorrectable error signal in response to the NOR output signal and the error detected signal, the uncorrectable error signal indicating the error in the second set of check bits and the second set of data is not correctable.”
However, Kaabouch, in analogous art, teaches wherein the error detection/correction logic circuit further comprises: a NOR logic gate coupled to the syndrome decoder, and configured to generate a NOR output signal in response to the error signal (comparator represented by the NAND gate 154 [Kaabouch PP 0021] the reference teaches a logic gate performing comparison, using NOR instead is obvious); and
an AND logic gate coupled to the OR logic gate and the NOR logic gate, and configured to generate an uncorrectable error signal in response to the NOR output signal and the error detected signal, the uncorrectable error signal indicating the error in the second set of check bits and the second set of data is not correctable (If the signatures do not match, then the security strategy preferably includes a security interrupt, security reset, or other mechanism [Kaabouch PP 0029], Based upon this comparison, the signature checker 150 outputs a security strategy 160 [Kaabouch PP 0021]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 14, Patange does not explicitly teach “wherein the syndrome generator comprises :a set of exclusive OR (XOR) trees coupled to the first set of inverters and configured to generate another set of check bits in response to the second set of data, each XOR tree of the set of XOR trees being configured to generate a corresponding check bit of the another set of check bits in response to the second set of data; and a set of XOR gates coupled to the set of XOR trees and the second memory cell array, and configured to generate the syndrome vector in response to the second set of check bits and the another set of check bits, each XOR gate of the set of XOR gates being coupled to a corresponding XOR tree of the set of XOR trees, and configured to generate a corresponding syndrome bit of the syndrome vector.”
However, Bartling, in an analogous art, teaches wherein the syndrome generator comprises :a set of exclusive OR (XOR) trees coupled to the first set of inverters and configured to generate another set of check bits in response to the second set of data, each XOR tree of the set of XOR trees being configured to generate a corresponding check bit of the another set of check bits in response to the second set of data (Each IO driver section … may contain an XOR gate 1160 [Bartling PP 0090]); and
a set of XOR gates coupled to the set of XOR trees and the second memory cell array, and configured to generate the syndrome vector in response to the second set of check bits and the another set of check bits, each XOR gate of the set of XOR gates being coupled to a corresponding XOR tree of the set of XOR trees, and configured to generate a corresponding syndrome bit of the syndrome vector (The output of XOR gate 1160 that is in bit column 30 is the overall parity value for the row of data that was read from bit columns 0 : 30 and is used to compare to a parity value read from bit column 31 by parity error detector XNOR gate 1370 . If the overall parity value determined from the read data does not match the parity bit read from column 31 , then a parity error is indicated. [Bartling PP 0091]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 15, Patange significantly teaches wherein the ECC decoder comprises: a first logic circuit configured to determine if the integrated circuit has been attacked by the user by detecting an invalid codeword, the invalid codeword including the second set of check bits and the second set of data (checking the payload data using the second check data according to a first check mechanism [Patange PP 0009], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset [Patange PP 0052]).
As per claim 16, Patange does not explicitly teach “wherein the first logic circuit comprises: a second set of inverters coupled to the first set of inverters and being configured to generate a fourth set of data in response to the second set of data, the fourth set of data being inverted from the second set of data.”
However, Bartling, in an analogous art, teaches wherein the first logic circuit comprises: a second set of inverters coupled to the first set of inverters and being configured to generate a fourth set of data in response to the second set of data, the fourth set of data being inverted from the second set of data (the parity bit is read, inverted 1716 , and written back. [Bartling PP 0113]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 17, Patange in view of Bartling do not explicitly teach “wherein the first logic circuit further comprises: a first NOR logic circuit coupled to the second memory cell array and the second set of inverters, and configured to generate the been-attacked signal in response to the second set of check bits and the fourth set of data.”
However, Kaabouch, in analogous art, teaches wherein the first logic circuit further comprises: a first NOR logic circuit coupled to the second memory cell array and the second set of inverters, and configured to generate the been-attacked signal in response to the second set of check bits and the fourth set of data (comparator represented by the NAND gate 154 [Kaabouch PP 0021]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 18, Patange significantly teaches storing the second set of data in a first memory cell array, the first memory cell array being coupled to the first set of inverters (retrieving, by the memory controller, the payload data from the memory area [Patange PP 0009]);
determining, by a first logic circuit, whether the first memory cell array and the second memory cell array have been attacked by a user by detecting an invalid codeword, the invalid codeword including the third set of data and a second set of check bits, the second set of check bits corresponds to the first set of check bits stored in the second memory cell array, and the first logic circuit being coupled to the second set of inverters and the second memory cell array (checking the payload data using the second check data according to a first check mechanism [Patange PP 0009], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset [Patange PP 0052]).
Patange does not explicitly teach “a method of operating an integrated circuit, the method comprising: receiving, by a first set of inverters, a first set of data, and generating, a second set of data in response to the first set of data, the second set of data being inverted from the first set of data; storing a first set of check bits in a second memory cell array; generating, by a second set of inverters, a third set of data in response to a fourth set of data, the fourth set of data being inverted from the third set of data, and the fourth set of data corresponds to the second set of data stored in the first memory cell array, the second set of inverters being coupled to the first memory cell array;”
However, Bartling, in an analogous art, teaches a method of operating an integrated circuit, the method comprising: receiving, by a first set of inverters, a first set of data, and generating, a second set of data in response to the first set of data, the second set of data being inverted from the first set of data (Before storing the parity bit, it is inverted [Bartling PP 0024]);
generating, by a second set of inverters, a third set of data in response to a fourth set of data, the fourth set of data being inverted from the third set of data, and the fourth set of data corresponds to the second set of data stored in the first memory cell array, the second set of inverters being coupled to the first memory cell array (the parity bit is read, inverted 1716 , and written back. [Bartling PP 0113]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
Patange in view of Bartling do not explicitly teach “storing a first set of check bits in a second memory cell array”
However, Kaabouch, in analogous art, teaches storing a first set of check bits in a second memory cell array (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
As per claim 19, Patange significantly teaches further comprising: decoding, by an ECC decoder, at least the third set of data or the second set of check bits thereby generating at least a set of output data or a been-attacked signal, the been-attacked signal indicating a reset attack by the user, and the ECC decoder being coupled to the second set of inverters and the second memory cell array (checking the payload data using the second check data according to a first check mechanism [Patange PP 0009], if multi-bit faults are detected on the data read from the non-volatile memory, it shall result in system reset [Patange PP 0052], data check module 19 implementing a first check mechanism and a second check mechanism [Patange PP 0046]).
As per claim 20, Patange does not explicitly teach “wherein determining whether the first memory cell array has been attacked by the user comprises: generating, by a third set of inverters, a fifth set of data in response to the third set of data, the fifth set of data being inverted from the third set of data, and the third set of inverters being coupled to the second set of inverters; and generating, by a NOR logic circuit, a been-attacked signal in response to the second set of check bits and the fifth set of data, the NOR logic circuit being coupled to the third set of inverters and the second memory cell array, the been-attacked signal indicating a reset attack by the user.”
However, Bartling, in an analogous art, teaches wherein determining whether the first memory cell array has been attacked by the user comprises: generating, by a third set of inverters, a fifth set of data in response to the third set of data, the fifth set of data being inverted from the third set of data, and the third set of inverters being coupled to the second set of inverters (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange to incorporate Bartling's teaching of reading and inverting stored check bits, in order to reliably recover the original check bits from the stored inverted form and ensure correct error detection (the parity bit is read, inverted 1716 , and written back [Bartling PP 0113]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
Patange in view of Bartling do not explicitly teach “generating, by a NOR logic circuit, a been-attacked signal in response to the second set of check bits and the fifth set of data, the NOR logic circuit being coupled to the third set of inverters and the second memory cell array, the been-attacked signal indicating a reset attack by the user.”
However, Kaabouch, in analogous art, teaches generating, by a NOR logic circuit, a been-attacked signal in response to the second set of check bits and the fifth set of data, the NOR logic circuit being coupled to the third set of inverters and the second memory cell array, the been-attacked signal indicating a reset attack by the user (comparator represented by the NAND gate 154 [Kaabouch PP 0021] the attack signal generation via comparison; using NOR is a straightforward design choice).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system disclosed by Patange in view of Bartling to incorporate Kaabouch's teaching of a separate checker memory for storing check bits, in order to securely store separate from memory (a checker memory 330 that is separate from the memory 310 [Kaabouch PP 0034]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Patange's invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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