Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 16/705,645, filed on 12/06/2019.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/19/2025 and 11/25/2025 were received. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 9 and 19 are objected to because of the following informalities: The examiner is unclear the scope of "lid". In light of the specification and figure 16B, the examiner has interpreted "lid" to mean an element physically on top, above, the disclosed chips.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 - 20, claim 1 as representative, the limitation “a silicon interposer” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of the term. Specifically, paragraph 0049, 0068, 0070, 0114, disclose language such as “the substrate BRD may be a silicon interposer”. However, the language fails to provide a scope or structure for “BRD” or “silicon interposer”.
Regarding claims 3 and 13, claim 3 as representative, the limitation “data” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear if applicant intended to refer to the data previously disclosed or additional data.
Regarding claims 5 and 15, claim 5 as representative, the limitation “a neural network” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “neural network”. Specifically, paragraphs 39 and 97 discloses “deep learning using a neural network”, however the language “a neural network” is so broad as to leave one of ordinary skill in the art unable to know the scope of what “arithmetic operations” may be performed.
Regarding claims 7 and 17, claim 7 as representative, the limitation “data” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear if applicant intended to refer to the data previously disclosed or additional data.
Regarding claims 9 and 19, claim 9 as representative, the limitation “continuously covered” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear how “continuously” modifies “covered” in relation to the lid.
Regarding claims 10 and 20, claim 10 as representative, the limitation “continuously sealed” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear how “continuously” modifies “sealed” in relation to the grease.
Any claim not addressed above is rejected due to its dependency on a rejected claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 – 3, 6, 11 – 13, and 16 are rejected on the ground of nonstatutory double patenting over claims 1 – 3 of U.S. Patent No. 12,255,149 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/057103
Claim 1 – Patent 12,255,149
A semiconductor device comprising:
A semiconductor device, comprising:
a first chip; and
a first chip;
a second chip
a second chip;
a third chip; and
a fourth chip, wherein
placed adjacent to the first chip,
the first chip is placed adjacent to the second chip and the fourth chip,
the third chip is placed adjacent to the second chip and the fourth chip at a position different from a position of the first chip,
wherein the first chip transfers data to the second chip via a silicon interposer,
data of the first chip is transferred from the first chip to the third chip via the second chip,
data of the third chip is transferred from the third chip to the first chip via the fourth chip, and
the data transferred to the second chip from the first chip via the silicon interposer is used in an arithmetic operation by an internal circuit of the second chip, and a layout design of the first chip is the same as a layout design of the second chip.
data of the first chip transferred from the first chip to the third chip via the second chip and used in an arithmetic operation by an internal circuit of the third chip is not used in an arithmetic operation by an internal circuit of the second chip.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/057103 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,255,149. Specifically, both claim 1, of the current application 19/057103, and claim 1, of patent 12,255,149 discloses: A semiconductor device, comprising “a first chip”, “a second chip”, and data “used in an arithmetic operation by an internal circuit”.
One of ordinary skill in the art would recognize the semiconductor device disclosed by claim 1, of the current application 19/057103, as a broad recitation of the operations performed by the semiconductor device disclosed in claim 1 of Patent 12,255,149. A semiconductor device performing operations and a semiconductor device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the semiconductor device claim 1, of the current application 19/057103, as performing the operations of the semiconductor device of claim 1, of U.S. Patent 12,255,149, and as such are obvious variants of each other.
Claim 2 – Application 19/057103
Claim 2 – Patent 12,255,149
Claim 3 – Application 19/057103
Claim 3 – Patent 12,255,149
Claim 6 – Application 19/057103
Claim 1 – Patent 12,255,149
Claim 11 – Application 19/057103
Claim 1 – Patent 12,255,149
Claim 12 – Application 19/057103
Claim 2 – Patent 12,255,149
Claim 13 – Application 19/057103
Claim 3 – Patent 12,255,149
Claim 16 – Application 19/057103
Claim 1 – Patent 12,255,149
Claims 1 – 4, 9 – 14, 19, and 20 are rejected on the ground of nonstatutory double patenting over claims 1 – 3 and 10 – 12 of U.S. Patent No. 11,824,009 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/057103
Claim 1 – Patent 11,824,009
A semiconductor device comprising:
A semiconductor device, comprising:
a first chip; and
a first chip;
a second chip
a second chip;
a third chip, and
a fourth chip,
placed adjacent to the first chip,
wherein the first chip is placed adjacent to the second chip and the fourth chip,
the third chip is placed adjacent to the second chip and the fourth chip at a position different from that of the first chip,
wherein the first chip transfers data to the second chip via a silicon interposer,
the second chip includes a first transferring circuit that transfers data received from the first chip to the third chip via a wiring layer formed over a silicon and placed at a position different from the first chip, the second chip, the third chip, and the fourth chip
the data transferred to the second chip from the first chip via the silicon interposer is used in an arithmetic operation by an internal circuit of the second chip, and a layout design of the first chip is the same as a layout design of the second chip.
without performing an arithmetic operation on the data received from the first chip, the first transferring circuit being placed in the second chip.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/057103 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,824,009. Specifically, both claim 1, of the current application 19/057103, and claim 1, of patent 11,824,009 discloses: A semiconductor device, comprising “a first chip”, “a second chip”, and data “used in an arithmetic operation by an internal circuit”.
One of ordinary skill in the art would recognize the semiconductor device disclosed by claim 1, of the current application 19/057103, as a broad recitation of the operations performed by the semiconductor device disclosed in claim 1 of Patent 11,824,009. A semiconductor device performing operations and a semiconductor device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the semiconductor device claim 2, of the current application 19/057103, as performing the operations of the apparatus of claim 2, of U.S. Patent 11,824,009, and as such are obvious variants of each other.
Claim 2 – Application 19/057103
Claim 2 – Patent 11,824,009
Claim 3 – Application 19/057103
Claim 3 – Patent 11,824,009
Claim 4 – Application 19/057103
Claim 11 – Patent 11,824,009
Claim 9 – Application 19/057103
Claim 10 – Patent 11,824,009
Claim 10 – Application 19/057103
Claim 12 – Patent 11,824,009
Claim 11 – Application 19/057103
Claim 1 – Patent 11,824,009
Claim 12 – Application 19/057103
Claim 2 – Patent 11,824,009
Claim 13 – Application 19/057103
Claim 3 – Patent 11,824,009
Claim 14 – Application 19/057103
Claim 11 – Patent 11,824,009
Claim 19 – Application 19/057103
Claim 10 – Patent 11,824,009
Claim 20 – Application 19/057103
Claim 12 – Patent 11,824,009
Closest Prior Arts of Record
Jo, U.S. Publication 2017/0154868, teaches: A semiconductor device comprising: a first chip; and a second chip placed adjacent to the first chip, wherein the first chip transfers data to the second chip via a silicon interposer, the data transferred to the second chip from the first chip (figure 2).
However, Jo fails to specifically teach: a layout design of the first chip is the same as a layout design of the second chip.
Lee, U.S. Publication 2017/0060801 (herein Lee), teaches: A semiconductor device comprising: a first chip; and a second chip placed adjacent to the first chip, wherein the first chip transfers data to the second chip via a silicon interposer, the data transferred to the second chip from the first chip (figure 2).
However, Lee fails to specifically teach: the data transferred to the second chip from the first chip via the silicon interposer is used in an arithmetic operation by an internal circuit of the second chip.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fricker; Jean-Philippe US 20200051890 A1
KOYANAGI; Masaru US 20200020670 A1
OH; SEONG HWAN et al. US 20190295986 A1
KIM; YONG HOON US 20190244946 A1
CHOI; Min Seok et al. US 20180074895 A1
YUN; Jae Woong et al. US 20180067801 A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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