Prosecution Insights
Last updated: October 02, 2026
Application No. 19/057,711

STANDBY EXIT FOR MEMORY DIE STACK

Non-Final OA §DP
Filed
Feb 19, 2025
Priority
Apr 19, 2022 — continuation of 12/254,948
Examiner
BASHAR, MOHAMMED A
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
641 granted / 674 resolved
+35.1% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
22 currently pending
Career history
696
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
4.8%
-35.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 674 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-24 of U.S. Patent No. 12254948. Current Application # 1905771 US Pat # 12254948 For example: 1. A memory system comprising: a first memory device coupled to a host device using a memory interface that includes a command line, a standby exit line, and a chip select line, the first memory device comprising at least a primary die and multiple secondary dies coupled using an intra-package bus, wherein communication between the first memory device and the host device is via the primary die and the memory interface, wherein the primary die has a first identifier and each of the secondary dies has a respective different identifier; wherein, in response to a state change on the standby exit line, the first memory device is configured to perform operations comprising: receive a standby exit command via the command line of the memory interface; determine if the standby exit command includes the first identifier; and in response to the standby exit command including the first identifier, exit a standby state and provide a subsequent standby exit command to the secondary dies using the intra-package bus. For example: 17. A memory system comprising: a host device; a first memory device coupled to the host device using a memory interface that includes a command line and a standby exit line, the first memory device comprising at least a primary die and multiple secondary dies coupled using an intra-package bus, wherein communication between the first memory device and the host device is exclusively via the primary die and a shared inter-device bus, wherein each secondary die of the multiple secondary dies is separately addressable, and wherein the first memory device has a first identification; and a second memory device coupled to the host device using the memory interface, wherein the second memory device has a second identification; wherein the host device is configured to perform operations comprising: changing a state on the standby exit line; and commanding the first memory device to exit a standby state by sending a wakeup message, that includes the first identification, using the command line of the memory interface. 18. The memory system of claim 17, wherein the memory interface further includes a chip select line, and wherein the host device is configured to send the wakeup message in coordination with changing a state on the chip select line. 24. The memory system of claim 17, wherein the host device operation of commanding the first memory device to exit a standby state includes using the primary die to broadcast a standby exit command to the multiple secondary dies using the intra-package bus, wherein the standby exit command includes an identification, provided by the host device, indicating a selected one of the multiple secondary dies. Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “secondary dies has a respective different identifier” in current application 19057711 and the limitation “second memory device has a second identification” in US Pat # 12254948 are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. Claims 1-20 would be allowable if the double patenting rejection set forth in this office action is overcome. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Feb 19, 2025
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12749551
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION
2y 6m to grant Granted Sep 29, 2026
Patent 12744104
APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA
2y 7m to grant Granted Sep 22, 2026
Patent 12744064
MEMORY DEVICE RELATED TO SIGNAL TRANSMISSION
2y 2m to grant Granted Sep 22, 2026
Patent 12731643
METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL
3y 5m to grant Granted Sep 08, 2026
Patent 12731653
NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF
2y 2m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+3.3%)
1y 10m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 674 resolved cases by this examiner. Grant probability derived from career allowance rate.

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