Prosecution Insights
Last updated: October 04, 2026
Application No. 19/057,716

TEMPERATURE CONTROL DEVICE AND TEMPERATURE CONTROL SYSTEM FOR PROVIDING TEMPERATURE CONTROL SPACE FOR INDIVIDUAL SEMICONDUCTOR PRODUCT IN TEST OF SEMICONDUCTOR PRODUCT

Non-Final OA §102§103
Filed
Feb 19, 2025
Priority
Oct 24, 2024 — RE 10-2024-0146952
Examiner
VELEZ, ROBERTO
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ateco Inc.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
188 granted / 278 resolved
At TC average
Strong +21% interview lift
Without
With
+21.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
302
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 278 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 08/29/2025, 03/12/2026 and 06/04/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita (US Pat. 6,445,203). Regarding claim 1, Yamashita et al. teaches a temperature control system (10) for providing a temperature control space for an individual semiconductor product (2) in a test of a semiconductor product (as shown in fig. 5), the temperature control system comprising: an insert (16) configured to load the semiconductor product (2) into an accommodating space (19, for example) with open one surface (as shown in fig. 2-3); a test tray (TST) on which a plurality of the inserts (16) are loaded (as shown in fig. 10); a tester (5) configured to test the semiconductor product (2) through the insert (16) in a state where the test tray (TST) is mounted (as shown in fig. 1 and disclosed in col. 10, lines 29-37); and a temperature control device (as shown in fig. 1) in close contact with one surface of the test tray (TST) or the insert (16) in a state where the test tray (TST) is mounted on the tester (5) and configured to separate the accommodating space (19) from an external space and control temperature of the accommodating space (19). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2-3, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US Pat. 6,445,203) in view of Kiyokawa et al. (US PGPUB 2023/0023699). Regarding claim 2, Yamashita et al. teaches the limitations of claim 1, in addition, Yamashita et al. teaches wherein the temperature control device includes a packing block (30) in close contact with the test tray (TST) or the insert (16) (as shown in fig. 1 and 4) and formed with a discharge port (112) for discharging a temperature-controlled test gas into the accommodating space (19) (as shown in fig. 1 and 4, and disclosed in col. 16, lines 16-31). Yamashita et al. fails to specifically teach an exhaust port for exhausting the test gas from the accommodating space to the outside. However, Kiyokawa et al. teaches an exhaust port (65, 240) for exhausting the test gas from the accommodating space to the outside (as shown in fig. 14 and disclosed in para. 0072 and 0074). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the exhaust port for exhausting the test gas from the accommodating space to the outside as taught by Kiyokawa et al. with the invention of Yamashita et al. in order to accurately cool and/or heat the semiconductor product. Regarding claim 3, the combination of Yamashita et al. and Kiyokawa et al. teaches the limitations of claim 2, in addition, Yamashita et al. teaches wherein the temperature control device further includes an auxiliary fluid discharge pipe (110) disposed to penetrate the packing block (30) and configured to discharge an auxiliary fluid for temperature control into the accommodating space (19) (as shown in fig. 1 and disclosed in col. 14, lines 16-32). Regarding claim 13, the combination of Yamashita et al. and Kiyokawa et al. teaches the limitations of claim 2, in addition, Yamashita et al. teaches wherein the discharge port (112) is formed to be positioned on a central axis of an upper surface of the accommodating space (19) (as shown in fig. 3-4). Yamashita et al. fails to specifically teach wherein the discharge port and the exhaust port are formed to be positioned on a central axis of an upper surface of the accommodating space. However, Kiyokawa et al. teaches wherein the discharge port (64 and 230) and the exhaust port (65 and 240) are formed to be positioned on a central axis of an upper surface of the accommodating space (space in 600) (as shown in fig. 14). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the discharge port and the exhaust port formed to be positioned on a central axis of an upper surface of the accommodating space as taught by Kiyokawa et al. with the invention of Yamashita et al. in order to efficiently distribute the heating/colling gas. Regarding claim 15, Yamashita et al. teaches a temperature control device (10) providing a temperature control space for a semiconductor product (2), which approaches an insert (16) for loading a semiconductor product (2) into an accommodating space (19, for example) with open one surface (as shown in fig. 1 and 3-4) and separates the accommodating space (19) from an external space (as shown in fig. 1 and 3-4), the temperature control device (10) comprising: a packing block (30) that is in close contact with a test tray (TST) on which the insert (16) is loaded or the insert (16) (as shown in fig. 1 and 4), and has a discharge port (112) for discharging a temperature-controlled test gas into the accommodating space (19) (as shown in fig. 1 and 4, and disclosed in col. 16, lines 16-31). Yamashita et al. fails to specifically teach an exhaust port for exhausting the test gas from the accommodating space to the outside. However, Kiyokawa et al. teaches an exhaust port (65, 240) for exhausting the test gas from the accommodating space to the outside (as shown in fig. 14 and disclosed in para. 0072 and 0074). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the exhaust port for exhausting the test gas from the accommodating space to the outside as taught by Kiyokawa et al. with the invention of Yamashita et al. in order to accurately cool and/or heat the semiconductor product. Claims 4-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US Pat. 6,445,203) and Kiyokawa et al. (US PGPUB 2023/0023699) as applied to claim 2 above, and further in view of Saito (US PGPUB 2019/0302178). Regarding claim 4, the combination of Yamashita et al. and Kiyokawa et al. teaches the limitations of claim 2, in addition, Yamashita et al. teaches wherein the temperature control device further includes a gas circulator (124, 126, 128 and 130) configured to circulate the test gas and control temperature (as disclosed in col. 14, lines 44-67), and a duct block (62) configured to distribute and deliver the test gas delivered from the gas circulator (124, 126, 128 and 130) to a plurality of the packing blocks (30) (as shown in fig. 1). The combination of Yamashita et al. and Kiyokawa et al. fails to specifically teach deliver the test gas exhausted through the plurality of the packing blocks to the gas circulator. However, Saito teaches deliver the test gas exhausted through the plurality of the packing blocks (32) to the gas circulator (50) (as shown in fig. 1). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have deliver the test gas exhausted through the plurality of the packing blocks to the gas circulator as taught by Saito with the invention of the combination of Yamashita et al. and Kiyokawa et al. in order to efficiently recycling some of the distributed heating/cooling gas. Regarding claim 5, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 4, in addition, Yamashita et al. teaches wherein the temperature control device further includes a temperature measurement sensor (114) built into the packing block (30) or the duct block to measure temperature (as shown in fig. 3). Regarding claim 6, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 4, in addition, Yamashita et al. teaches wherein the temperature control device further includes a distribution plate (72) that forms a circulation path of the test gas between the plurality of duct blocks (62) and the gas circulator (124, 126, 128 and 130). Regarding claim 7, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 6, in addition, Yamashita et al. teaches wherein one surface of the distribution plate (72) facing the test tray (TST) is formed to have an extent (74) corresponding to the test tray (TST), and each of the duct blocks (62) is disposed on one surface of the distribution plate (72) to correspond to a different area of the test tray (TST) (as shown in fig. 1). Regarding claim 8, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 7, in addition, Yamashita et al. teaches wherein the temperature control device further includes a heat exchange unit (121) disposed in the duct block (62) and configured to control the temperature of the test gas distributed to the plurality of packing blocks (30) (as shown in fig. 1 and disclosed in col. 14, lines 16-32). Regarding claim 9, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 4, in addition, Yamashita et al. teaches wherein the temperature control device further includes a circulation chamber (90) in which the gas circulator (124, 126, 128 and 130) is disposed and which provides a space in which the test gas is circulated, so that the test gas waits in a temperature-controlled state (as shown in fig. 1). Regarding claim 10, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 9, in addition, Yamashita et al. teaches wherein the temperature control device further includes a dry chamber (102) that the circulation chamber (90) is disposed inside and which maintains temperature of an internal space within a predetermined range (as shown in fig. 1). Regarding claim 12, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 4, in addition, Yamashita et al. teaches wherein the duct block (62) includes a discharge flow path (116) extending straightly toward the packing block (30) and communicating with the discharge port (112) (as shown in fig. 3-4) and Saito teaches an exhaust flow path communicating with the exhaust port (415) and bent at least once inside the duct block (31 and 50) (as shown in fig. 1-2). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the exhaust flow path communicating with the exhaust port and bent at least once inside the duct block as taught by Saito with the invention of the combination of Yamashita et al. and Kiyokawa et al. in order to efficiently convey the distributed heating/cooling gas. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US Pat. 6,445,203), Kiyokawa et al. (US PGPUB 2023/0023699) and Saito (US PGPUB 2019/0302178) as applied to claim 9 above, and further in view of KIRIHARA et al. (TW 201710693 A). Regarding claim 11, the combination of Yamashita et al., Kiyokawa et al. and Saito teaches the limitations of claim 9, in addition, Yamashita et al. teaches wherein the temperature control device further includes a dry chamber (102) that the circulation chamber (90) is disposed inside. The combination of Yamashita et al., Kiyokawa et al. and Saito fails to specifically teach wherein the temperature control device further includes that humidity of an internal space is controlled. However, KIRIHARA et al. teaches wherein the temperature control device (29) further includes that humidity of an internal space is controlled (as disclosed in the description). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the temperature control device further include that humidity of an internal space is controlled as taught by KIRIHARA et al. with the invention of the combination of Yamashita et al., Kiyokawa et al. and Saito in order to prevent dew condensation and icing of the semiconductor product (KIRIHARA et al. description). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US Pat. 6,445,203) and Kiyokawa et al. (US PGPUB 2023/0023699) as applied to claim 1 above, and further in view of LEE (KR 102363332 B1). Regarding claim 14, the combination of Yamashita et al. and Kiyokawa et al. teaches the limitations of claim 1. The combination of Yamashita et al. and Kiyokawa et al. fails to specifically teach wherein the temperature control device further includes a packing member configured to seal a gap between the packing block and the insert in a state where the packing block is in close contact with the test tray or the insert. However, LEE teaches wherein the temperature control device further includes a packing member (624) configured to seal a gap between the packing block (500) and the insert in a state where the packing block is in close contact with the test tray or the insert (as shown in fig. 10). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the temperature control device further include a packing member configured to seal a gap between the packing block and the insert in a state where the packing block is in close contact with the test tray or the insert as taught by LEE with the invention of the combination of Yamashita et al. and Kiyokawa et al. in order to hermetically adhere the packing block to the insert or tray. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERTO VELEZ/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Feb 19, 2025
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
89%
With Interview (+21.4%)
2y 8m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 278 resolved cases by this examiner. Grant probability derived from career allowance rate.

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