DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt (KR10-2024-0105708) is acknowledged of certified copies of papers required by 37 CFR 1.55.
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 02/23/2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0026260 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2025/0252926) in view of Feng et al. (US 2021/0327339).
As to Claim 1, Kim discloses A driving circuit comprising a plurality of stages (fig.1,6; para.0130), wherein each of the plurality of stages comprises:
a first transistor (fig.6, transistor T13) connected to a first terminal receiving a start signal (fig.6, terminal VST), and to a first node (fig.6, node Q2), the first transistor comprising a gate connected to a clock terminal receiving a clock signal (fig.6, gate of T13 connected to clock signal CLK);
a second transistor (fig.6, transistor TA) connected between the first node (fig.6, node Q2) and a second node (fig.6, node Q), and comprising a gate connected to a second terminal receiving a first voltage (fig.6, gate of TA connected to gate low voltage VGL);
a third transistor (fig.6, transistor T16) connected between a third terminal receiving a second voltage higher than the first voltage (fig.6, terminal gate high voltage VGH), and a third node (fig.6, node QB), the third transistor comprising a gate connected to the first node (fig.6, gate of T16 connected to node Q2);
fourth transistor connected between the third node and the second terminal, and comprising a gate connected to the second node;
a fifth transistor (fig.6, transistor T11) connected between an output terminal (fig.6, output terminal SRO) and the second terminal (fig.6, terminal VGL), and comprising a gate connected to the second node (fig.6, gate of T11 connected to node Q);
a sixth transistor (fig.6, transistor T12) connected between the third terminal (fig.6, terminal VGH) and the output terminal (fig.6, output terminal SRO), and comprising a gate connected to the third node (fig.6, gate connected to node QB); and
a seventh transistor connected between the third node and the second terminal, and comprising a gate connected to a reset terminal.
Kim does not expressly disclose fourth transistor connected between the third node and the second terminal, and comprising a gate connected to the second node; a seventh transistor connected between the third node and the second terminal, and comprising a gate connected to a reset terminal.
Feng et al. discloses a shift register comprising a fourth transistor (fig.5, transistor M8) connected between the third node (fig.5, node PD) and the second terminal ( fig.5, terminal VGL), and comprising a gate connected to the second node (fig.5, gate of M8 connected to node PU).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim with the teachings of Feng et al., so that under the control of the pull up node (PU), the voltage of the voltage terminal VGL is continuously output to the pull down node (PD).
Kim in view of Feng et al. do not expressly disclose a seventh transistor connected between the third node and the second terminal, and comprising a gate connected to a reset terminal.
However, in Kim in view of Feng et al., Feng et al. discloses a reset circuit 103 to reset the pull-up node (para.0066-0068), the reset circuit including a seventh ta seventh transistor (fig.5, transistor M12) connected between second node (fig.5, node PU) and the second terminal (fig.5, terminal VGL), and comprising a gate connected to a reset terminal (fig.5, gate of M12 connected to reset terminal RST).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Kim in view of Feng et al. by implementing a reset circuit (as disclosed by Feng) such that it connects to the pull-down node PD, in order to transmit the voltage of low voltage VGL to the pull-down node and reset the pull-down node.
As to Claim 5, Kim in view of Feng et al. disclose wherein the third transistor is a P-channel transistor (Kim-fig.6, transistor T16), and the fourth transistor is an N-channel transistor (Feng-fig.5, transistor M8).
As to Claim 6, Kim in view of Feng et al. disclose wherein the fourth transistor is an N-channel transistor (Feng-fig.5, transistor M8; para.0087), and remaining transistors other than the fourth transistor are P-channel transistors (Kim-fig.6).
As to Claim 7, Kim in view of Feng et al. disclose wherein each of the plurality of stages further comprises: a first capacitor connected between the second node and the output terminal (Kim-fig.6, capacitor CQ between node Q and output SRO); and a second capacitor connected between the third terminal and the third node (Kim-fig.6, capacitor CQB between terminal VGH and third node QB).
Claim(s) 2,4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2025/0252926) in view of Feng et al. (US 2021/0327339), further in view of Wang et al. (US 2022/0398968)
As to Claim 2, Kim in view of Feng et al. do not expressly disclose, but Wang et al. discloses wherein, from a time when the first voltage and the second voltage are input to a time when the clock signal is input, a reset signal of a gate-on voltage is input to the reset terminal of each of the plurality of stages, and the third nodes of the plurality of stages are simultaneously reset to the first voltage (fig.18, para.0191, each register is reset during power-on stage)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Kim in view of Feng et al with the teachings of Wang et al., the motivation being to mitigate the problem that the signal output in the display phase is affected due to an abnormal potential of the pull-up node.
As to Claim 4, Kim in view of Feng et al., as modified by Wang et al. disclose wherein, when the start signal is input after the time when the clock signal is input, output signals are sequentially output from the output terminals of the plurality of stages, and a reset signal of a gate-off voltage is input to the reset terminal of each of the plurality of stages from the time when the clock signal is input (Feng-fig.8 -9; Wang-fig.13-16,18).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2025/0252926) in view of Feng et al. (US 2021/0327339), further in view of Wang et al. (US 2021/0118347, hereafter Want347).
As to Claim 8, Kim in view of Feng et al. disclose where the seventh transistor is N-channel transistor (Feng- fig.6, transistor M12). Kim in view of Feng et al. do not expressly disclose, but Wang347 discloses: wherein each of the plurality of stages further comprises an eighth transistor (fig.10, transistor M15) connected between the third terminal (fig.10, node QB) and the first node (fig.10, node NA), and comprising a gate connected to the reset terminal (fig.10, gate of M15 connected to CLK3 (reset signal); para.0114-0115,0117), wherein the eighth transistor are N-channel transistors (fig.10, transistor M15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Kim in view of Feng et al with the teachings of Wang347, the motivation being to avoid leakage of the pull-up node, thereby ensuring output stability.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0172659) in view of He (US 2015/0029083).
As to Claim 17, Park et al. discloses An electronic device comprising: a controller configured to output a plurality of clock signals (fig.1, controller 130; para.0045-0046);
a power supply circuit configured to output a plurality of voltages (fig.2, voltages VGL, VGH); and
a driving circuit configured to output a gate signal based on the plurality of clock signals and the plurality of voltages (fig.1-2, gate driver GD; para.0064),
wherein the driving circuit comprises a plurality of stages, wherein each of the plurality of stages comprises:
a first transistor (fig.3, transistor T1) connected to a first terminal receiving a start signal (fig.1, start terminal Vst1), and to a first node (fig.3, node between T1 and T2), the first transistor comprising a gate connected to a clock terminal receiving one of the clock signals (fig.3, gate of T1 connected to GCLK1);
a second transistor (fig.3, transistor T2) connected between the first node (fig.6, node between T1 and T2) and a second node (fig.3, node Q), and comprising a gate connected to a second terminal receiving a first voltage among the plurality of voltages (fig.3, gate of T2 connected to VGL);
an inverter (fig.3, transistors T3, T4) connected between a third terminal receiving a second voltage among the plurality of voltages (fig.3, terminal VGH), and the second terminal (fig.3, terminal VGL), the inverter being configured to control a voltage of a third node node to be a voltage obtained by inverting a voltage level of the first node or the second node (para.0117, A high level voltage VGH may be provided to the QB node {third node} by the turned-on fourth transistor T4, a p-type transistor, which is turned on by low level voltage of the Q node);
a pull-down transistor (fig.3, transistor T7, pull down unit PD, para.0081) connected between an output terminal (fig.3, output terminal Vgout) and the second terminal (fig.3, terminal VGL), and comprising a gate connected to the second node (fig.3, node of T7, connected to node Q);
a pull-up transistor (fig.3, transistor T8, pull up unit PU, para.0083) connected between the third terminal (fig.3m terminal VGH) and the output terminal (fig.3, terminal Vgout), and comprising a gate connected to the third node (fig.3, node QB); and
a reset circuit configured to reset the second node or the third node.
Park et al. does not expressly disclose, but He discloses a power supply circuit configured to output a plurality of voltages (fig.1, voltage generating unit 600; para.0089); a reset circuit configured to reset the second node or the third node (fig.6, para.0161- transistor TA6 discharges the pull up node PU to the gate off voltage Vgoff in response to reset signal FR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Park et al. with the teachings of He, the motivation being to generate power supply voltages and discharge the second node (PU) under the control of reset signal, aiding in settling vertical mura, thereby improving the image quality of the display device.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0172659) in view of He (US 2015/0029083), further in view of Liu et al. (US 2021/0241673).
As to Claim 18, Park et al. in view of He do not expressly disclose but Liu et al. discloses: wherein the reset circuit comprises a third transistor (fig.9, transistor T17) connected between the third node (fig.9 node PD) and the second terminal (fig.9, second electrode of transistor T17 may be connected to low voltage terminal, VGL; para.0105), and comprising a gate connected to a reset terminal (fig.9, gate of T17 connected to reset Rst terminal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of He, with the teachings of Liu et al., the motivation being to control the potential of the third node (node PD) to a valid voltage under the control of a reset signal.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0172659) in view of He (US 2015/0029083), in view Liu et al. (US 2021/0241673), further in view of Kim (US 2025/0252926).
As to Claim 19, Park et al. in view of He do not expressly disclose, wherein the reset circuit comprises: a third transistor connected between the third node and the second terminal, and comprising a gate connected to a reset terminal; and a fourth transistor connected between the third terminal and the first node, and comprising a gate connected to the reset terminal, wherein the third transistor and the fourth transistor are N-channel transistors.
Liu et al. discloses wherein the reset circuit comprises: a third transistor (fig.9, transistor T17) connected between the third node (fig.9 node PD) and the second terminal (fig.9, second electrode of transistor T17 may be connected to low voltage terminal; para.0105), and comprising a gate connected to a reset terminal (fig.9, gate of T17 connected to reset Rst terminal), where the third transistor is an N channel transistor (fig.9, transistor T17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of He, with the teachings of Liu et al., the motivation being to control the potential of the third node (node PD) to a valid voltage under the control of a reset signal.
Park et al. in view of He, as modified by Liu et al. do not expressly disclose, but Kim discloses a reset circuit comprises: a fourth transistor (fig.6, transistor T17) connected between the third terminal (fig.6, terminal VGH) and the first node (fig.6, node Q2), and comprising a gate connected to the reset terminal (fig.6, gate of T17 connected to Reset terminal), wherein the fourth transistor is N-channel transistor (para.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of He, as modified by Liu et al., with the teachings of Kim, the motivation being to enhance the voltage of Q node (second node) in response to a reset signal, thereby securing stable output of the scan signal or emission signal in abnormal off/on situations (para.0196,0219-0220).
As to Claim 20, Park et al. in view of He do not expressly disclose wherein the reset circuit comprises: a third transistor connected between the third node and a fourth terminal receiving a third voltage among the plurality of voltages, the third transistor comprising a gate connected to a reset terminal; and a fourth transistor connected between the third terminal and the first node, and comprising a gate connected to the reset terminal, wherein the third transistor and the fourth transistor are N-channel transistors.
Liu et al. discloses wherein the reset circuit comprises: a third transistor (fig.9, transistor T17) connected between the third node (fig.9 node PD) and a fourth terminal receiving a third voltage among the plurality of voltages (fig.9, second electrode of transistor T17 may be connected to a low voltage terminal; para.0105), and comprising a gate connected to a reset terminal (fig.9, gate of T17 connected to reset Rst terminal), where the third transistor is an N channel transistor (fig.9, transistor T17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of He, with the teachings of Liu et al., the motivation being to control the potential of the third node (node PD) to a valid voltage under the control of a reset signal.
Park et al. in view of He, as modified by Liu et al. do not expressly disclose, but Kim discloses a reset circuit comprises: a fourth transistor (fig.6, transistor T17) connected between the third terminal (fig.6, terminal VGH) and the first node (fig.6, node Q2), and comprising a gate connected to the reset terminal (fig.6, gate of T17 connected to Reset terminal), wherein the fourth transistor is N-channel transistor (para.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of He, as modified by Liu et al., with the teachings of Kim, the motivation being to enhance the voltage of Q node (second node) in response to a reset signal, thereby securing stable output of the scan signal or emission signal in abnormal off/on situations (para.0196,0219-0220).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0172659) in view of Lim et al. (US 2015/0206490), further in view of Liu et al. (US 2021/0241673).
As to Claim 22, Park et al. discloses An electronic device comprising: a controller configured to receive an on-operation signal from a processor and output a reset signal based on the on-operation signal (fig.1, controller 130; para.0044,0046); and
a driving circuit comprising a stage configured to receive the reset signal and reset a control node (fig.1-2, gate driver GD; para.0064), wherein the stage comprises:
a first transistor (fig.3, transistor T1) connected to a first terminal receiving a start signal (fig.1, start terminal Vst1), and to a first node (fig.3, node between T1 and T2), the first transistor comprising a gate connected to a clock terminal receiving a clock signal (fig.3, gate of T1 connected to GCLK1);
a second transistor (fig.3, transistor T2) connected between the first node (fig.6, node between T1 and T2) and a second node (fig.3, node Q), and comprising a gate connected to a second terminal receiving a first voltage (fig.3, gate of T2 connected to VGL);
an inverter (fig.3, transistors T3, T4) connected between a third terminal receiving a second voltage (fig.3, terminal VGH), and the second terminal (fig.3, terminal VGL), the inverter being configured to control a voltage of the control node to be a voltage obtained by inverting a voltage level of the first node or the second node (para.0117, A high level voltage VGH may be provided to the QB node by the turned-on fourth transistor T4, a p-type transistor, which is turned on by low level voltage of the Q node);
a pull-down transistor (fig.3, transistor T7, pull down unit PD, para.0081) connected between an output terminal (fig.3, output terminal Vgout) and the second terminal (fig.3, terminal VGL), and comprising a gate connected to the second node (fig.3, node of T7, connected to node Q);
a pull-up transistor (fig.3, transistor T8, pull up unit PU, para.0083) connected between the third terminal (fig.3m terminal VGH) and the output terminal (fig.3, terminal Vgout), and comprising a gate connected to the control node (fig.3, node QB); and
a reset transistor connected between the control node and the second terminal, and comprising a gate connected to a reset terminal receiving the reset signal.
Park et al. does not expressly disclose a controller configured to receive an on-operation signal from a processor and output a reset signal based on the on-operation signal; a driving circuit comprising a stage configured to receive the reset signal and reset a control node; a reset transistor connected between the control node and the second terminal, and comprising a gate connected to a reset terminal receiving the reset signal.
Lim et al. discloses a controller configured to receive an on-operation signal from a processor and output a reset signal based on the on-operation signal (fig.1, para.0028-0029,0047,0139-0140; timing controller 200 receives input image RGB and control signal CONT from an external apparatus, and a reset circuit is operated based on the received input image, where when input image data represents a video image, the reset signal may have a low level; and when the input image data represents a static image, the reset signal the reset signal may periodically increase to a high level from the low level); a driving circuit comprising a stage configured to receive the reset signal and reset a control node (fig.1-2, gate driver 300; para.0029-0030, 0063-0065).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Park et al. with the teachings of Lim et al., the motivation being to provide resetting operation based on input image, and improve reliability of the gate driving circuit and quality of the display panel.
Park et al. in view of Lim et al. disclose a reset transistor (Lim-fig.2, reset part 390; para.0073).
Park et al. in view of Lim do not expressly disclose, but Liu et al. discloses: a reset transistor (fig.9, transistor T17) connected between the control node (fig.9 node PD) and the second terminal (fig.9, second electrode of transistor T17 may be connected to low voltage terminal, VGL; para.0105) , and comprising a gate connected to a reset terminal receiving the reset signal (fig.9, gate of T17 connected to reset Rst terminal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of Lim et al., with the teachings of Liu et al., the motivation being to control the potential of the control node (node PD) to a valid voltage under the control of the reset signal.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0172659) in view of Lim et al. (US 2015/0206490), further in view of Liu et al. (US 2021/0241673), and further in view of Wang et al. (US 2021/0118347).
As to Claim 8, Park et al. in view of Lim et al., as modified by Liu et al. disclose where the first reset transistor is N-channel transistor (Liu-fig.9, transistor T17).
Park et al. in view of Lim et al., as modified by Liu et al. do not expressly disclose, but Wang et al. discloses: wherein the stage further comprises a second reset transistor (fig.10, transistor M15) connected between the third terminal (fig.10, node QB) and the first node (fig.10, node NA), and comprising a gate connected to the reset terminal (fig.10, gate of M15 connected to CLK3 (reset signal); para.0114-0115,0117), wherein the second reset transistor is N-channel transistor (fig.10, transistor M15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device disclosed by Park et al. in view of Lim et al., as modified by Liu et al. with the teachings of Wang et al., the motivation being to avoid leakage of the pull-up node, thereby ensuring output stability.
Allowable Subject Matter
Claims 10-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent Claim 10 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “a driving circuit comprising “fourth transistor connected between the third node and the second terminal, and comprising a gate connected to the second node; a fifth transistor connected between an output terminal and the second terminal and comprising a gate connected to the second node, a sixth transistor connected between the third terminal and the output terminal and comprising a gate connected to the third node; and a seventh transistor connected between the third node and a fourth terminal receiving a third voltage lower than the first voltage, the seventh transistor comprising a gate connected to a reset terminal; and an eighth transistor connected between the third terminal and the first node, and comprising a gate connected to the reset terminal” in combination with the other limitations in the claim.
Claim 3, 9, 21, 24 are is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “for a certain period of time before the time when the first voltage and the second voltage are input, 0 volts (V) is input to the first terminal, the second terminal, the third terminal, and the reset terminal of each of the plurality of stages, and the third nodes of the plurality of stages are simultaneously discharged to 0 V” along with the other limitations in the claim.
Claim 9 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein each of the plurality of stages further comprises an eighth transistor connected between the third terminal and the first node, and comprising a gate connected to a second reset terminal, wherein the seventh transistor is a P-channel transistor and the eighth transistor is an N-channel transistor, wherein a timing at which a first reset signal input to the reset terminal connected to the seventh transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal connected to the eighth transistor is the gate-on voltage are the same” along with the other limitations in the claim.
Claim 21 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the reset circuit comprises: a third transistor connected between the third node and the second terminal, and comprising a gate connected to a first reset terminal; and a fourth transistor connected between the third terminal and the first node, and comprising a gate connected to a second reset terminal, wherein the third transistor is a P-channel transistor, and the fourth transistor is an N-channel transistor, wherein a timing at which a first reset signal input to the first reset terminal of the third transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal of the fourth transistor is a gate-on voltage are the same” along with the other limitations in the claim.
Claim 24 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the stage further comprises a second reset transistor connected between the third terminal and the first node, and comprising a gate connected to a second reset terminal, wherein the reset transistor is a P-channel transistor, and the second reset transistor is an N-channel transistor, wherein the controller is further configured to control a timing at which a reset signal input to the reset terminal of the reset transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal of the second reset transistor is a gate-on voltage to be the same” along with the other limitations in the claim.
Conclusion
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/DISMERY MERCEDES/ Primary Examiner, Art Unit 2627