DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1, 13 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xi et al (US 2023/0089185).
Claim 1, 13 & 15, Xie (Fig. 1-2) show an integrated CFET (or complementary field-effect transistor device) which could be utilized in any general semiconductor applications including memory chips and/or other chip package as well-known in this art. This CFET device includes at least one p-type transistor layer 104 (or 205, Fig. 2 below) comprising p-type transistors , see para [0071 to 0075] disclosure, and one n-type transistor layer comprising n-type transistors 108 (or 209), wherein the n-type transistor layer is above the p-type transistor layer; see [0073] stated that bottom layer is P-Type and top layer is N-Type as claimed, and Fig. 2 shows at least one intermediate/vertical layer (244/246) as the claimed “one or more intermediate metal layers” between the p-type transistor layer and the n-type transistor layer for coupling the bottom layer 212 (left side) to the top layer 234 (right side), wherein the one or more intermediate metal layers are coupled to the p-type transistor layer and to the n-type [AltContent: textbox (At least one intermediate layer 244/246 for connecting two layers N-P)]transistor layer through this intermediate/vertical layer as seen by a skilled person in this [AltContent: arrow]art.
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Top N-Type layer 209)][AltContent: textbox (Bottom P-Type layer 205)]
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3. Claims 1, 13 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reznicek et al (2019/0131394).
Claim 1, 13 & 15, Reznicek (see Fig. 11) show an integrated CFET (or complementary field-effect transistor device) which could be utilized in any general semiconductor applications including memory SRAM chips and/or other chip package as well-known in this art. This CFET device includes at least one p-type transistor layer 22S at bottom comprising only p-type transistors (or pFET), see disclosure, and one n-type transistor layer 26S comprising only n-type transistors 108 (or nFET), wherein the n-type transistor layer is above the p-type transistor layer, and that Fig. 11 also shows at least two intermediate/vertical layer 28 (on both left & right sides)) as the claimed “one or more intermediate metal layers” between the p-type transistor layer and the n-type transistor layer for coupling the bottom layer 22S (to the top layer 26S as claimed, wherein the one or more intermediate metal layers are coupled to the p-type transistor layer and to the n-type transistor layer through this intermediate/vertical layer as seen by a skilled person in this art.
[AltContent: textbox (At least one intermediate layers 36 for connecting two different epitaxy layers N-P)]
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[AltContent: arrow][AltContent: arrow][AltContent: textbox (Top N-Type layer 26S)][AltContent: textbox (Bottom P-Type layer 22S)]
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Allowable Subject Matter
4. The claims 16-20 are allowable over the prior arts of record. Additionally, other clams 2-12 & 14 are objected as being dependent upon the rejcted claims above, but they tentatively contain additional/novel limitations to the recited structure above, which are all neither suggested by eth prior arts nor seen elsewhere at this time.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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