DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 2022/0366847).
Regarding claim 1, An discloses a display device (100, fig. 1, para. 0086) comprising:
a substrate (1000, fig. 11, para. 0210) comprising a display area (DA, PA) comprising emission areas (DA) and a non-display area (PA) disposed around the display area;
a circuit layer (PCL, fig. 10, para. 0198) disposed on the substrate; and
an element layer (EDL, fig. 10, para. 0198) disposed on the circuit layer,
wherein the display area comprises a main display area (AR1, para. 0190) in which the emission areas are arranged side by side, and at least one sub-display area (AR2, para. 0190) surrounded by the main display area,
each of the at least one sub-display area further comprises light transmission areas (TA, para. 0210) disposed between the emission areas,
the element layer (EDL) comprises:
main light emitting elements (DE1, fig. 10, para. 0200) disposed in the emission areas of the main display area (AR1); and
sub-light emitting elements (DE2, fig. 10, para. 0200) disposed in the emission areas of the at least one sub-display area (AR2), and
the circuit layer (PCL) comprises:
main light emitting pixel drivers (PC1, fig. 2, para. 0119) electrically connected to the main light emitting elements (DE1);
sub-light emitting pixel drivers (PC2, fig. 2, para. 0119) electrically connected to the sub-light emitting elements (DE2);
a main anode initialization voltage line (VL1, paras. 0218 and 0223) disposed in the main display area (AR1) and configured to transmit a main anode initialization voltage (VINT1) for initializing the main light emitting elements (DE1); and
a sub-anode initialization voltage line (VL2, paras. 0218 and 0223) disposed in the at least one sub-display area (AR2) and configured to transmit a sub-anode initialization voltage (VINT2) for initializing the sub-light emitting elements.
Regarding claims 2 and 16, An discloses the sub-anode initialization voltage (VINT2) has a voltage level different from the main anode initialization voltage (VINT1) (para. 0218).
Regarding claims 3 and 17, An discloses a width of each of the sub-light emitting elements is greater than a width of each of the main light emitting elements (para. 0214), and
the sub-anode initialization voltage has a voltage level lower than the main anode
initialization voltage (para. 0010).
Regarding claims 4 and 18, An discloses the circuit layer further comprises:
a main anode initialization voltage supply line (11, fig. 11, para. 0215) disposed in the non-display area (PA) and electrically connected to the main anode initialization voltage line (VL1); and
a sub-anode initialization voltage supply line (12, fig. 11, para. 0215) disposed in the non-display area (PA) and configured to transmit the sub-anode initialization voltage (VL2).
Regarding claims 5 and 19, An discloses the circuit layer further comprises:
a sub-anode initialization voltage outer line (VL2b, para. 0221) extending along an edge of the at least one sub-display area; and
at least one sub-anode initialization voltage connection line (VL2c, para. 0221) electrically connecting the sub-anode initialization voltage supply line to the sub-anode initialization voltage outer line.
Regarding claims 6 and 20, An discloses the circuit layer further comprises:
a sub-anode initialization voltage transmission line (VL2a, para. 0221) disposed in the at least one sub-display area, extending in a direction intersecting the sub-anode initialization voltage line, and electrically connected to the sub-anode initialization voltage outer line and the sub-anode initialization voltage line.
Regarding claim 7, An discloses the circuit layer further comprises:
a sub-anode initialization voltage additional line (VL2b, para. 0221) disposed in the at least one sub-display area, extending in a direction intersecting the sub-anode initialization voltage transmission line, and electrically connected to the sub-anode initialization voltage transmission line.
Regarding claim 8, An discloses the circuit layer further comprises:
data lines for transmitting a data signal;
first auxiliary lines (VL3, paras. 0228-0230) extending in a first direction intersecting the data lines; and
second auxiliary lines (VL4, para. 0231) extending in a second direction parallel to the data lines and adjacent to the data lines, wherein the first auxiliary lines comprise the sub-anode initialization voltage additional line.
Regarding claim 9, An discloses the second auxiliary lines (VL4, para. 0231) comprise the at least one sub-anode initialization voltage connection line.
Regarding claim 10, An discloses the first auxiliary lines (VL3, paras. 0228-0230) further comprise the at least one sub-anode initialization voltage connection line.
Regarding claim 15, An discloses a display device (100, fig. 1, para. 0086) comprising:
a substrate (1000, fig. 11, para. 0210) comprising a display area (DA, PA) comprising emission areas (DA) and a non-display area (PA) disposed around the display area;
a circuit layer (PCL, fig. 10, para. 0198) disposed on the substrate; and
an element layer (EDL, fig. 10, para. 0198) disposed on the circuit layer,
wherein the display area comprises a main display area (AR1, para. 0190) in which the emission areas are arranged side by side, and at least one sub-display area (AR2, para. 0190) surrounded by the main display area,
each of the at least one sub-display area further comprises light transmission areas (TA, para. 0210) disposed between the emission areas,
the element layer (PCL) comprises:
main light emitting elements (DE1, fig. 10, para. 0200) disposed in the emission areas of the main display area (AR1); and
sub-light emitting elements (DE2, fig. 10, para. 0200) disposed in the emission areas of the at least one sub-display area (AR2), and
the circuit layer (PCL) comprises:
main light emitting pixel drivers (PC1, fig. 2, para. 0119) electrically connected to the main light emitting elements (DE1);
sub-light emitting pixel drivers (PC2, fig. 2, para. 0119) electrically connected to the sub-light emitting elements (DE2);
a main anode initialization voltage line (VL1, paras. 0218 and 0223) disposed in the main display area (AR1) and configured to transmit a main anode initialization voltage (VINT1) for initializing the main light emitting elements (DE1); and
a sub-anode initialization voltage line (VL2, paras. 0218 and 0223) disposed in the at least one sub-display area (AR2) and configured to transmit a sub-anode initialization voltage (VINT2) for initializing the sub-light emitting elements (DE2).
Allowable Subject Matter
Claims 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 11 identifies the distinct limitations “a bypass area on one side of the main display area comprises a bypass middle area, a first bypass side area parallel to the bypass middle area in the first direction and adjacent to the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area…a second data supply line, which transmits a data signal of the second data line among the data supply lines, is directly electrically connected to the second data line”. Claims 12 and 13 identify the distinct limitations “an eighth transistor electrically connected between a bias voltage line for transmitting a bias voltage and the first electrode of the first transistor”. Claim 14 identifies the distinct limitations “a first main anode initialization voltage line configured to transmit a first main anode initialization voltage for initializing the main light emitting element of the first emission area and the main light emitting element of the third emission area…a second sub-anode initialization voltage line configured to transmit a second sub-anode initialization voltage for initializing the sub-light emitting element of the second emission area”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Li et al. (US 2026/0020453) disclose display panel 100 includes an active area AA and a peripheral area BB surrounding the active area AA, the active area AA may include a light-transmitting active area 110, The first active area 120 and the second active area 130 extend laterally along the display panel 100, and the second active area 130, initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL (fig. 1, para. 0074 and 0118).
Ma et al. (US 2022/0077265) disclose display panel has a display region 1 includes an optical component setting region 2. The optical component setting region 2 at least partially overlaps an optical component (such as a camera or an infrared light sensor). The optical component setting region 2 includes a plurality of pixel regions 3. A light transmission region 4 is formed between adjacent pixel regions 3 (fig. 3, para. 0017).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER T NGUYEN whose telephone number is (571)272-7696. The examiner can normally be reached Mon-Fri 7:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 5712722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JENNIFER T NGUYEN/ Primary Examiner, Art Unit 2629