DETAILED ACTION
Claims 1-5, 7-8 and 16-20 are amended. Claims 11-15 are withdrawn. Claims 1-10 and 16-20 are pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LIGHT EMITTING LED DISPLAY DEVICE REDUCING POWER CONSUMPTION AND DEAD SPACE OF THE LED DISPLAY DEVICE
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20230075763) in view of Park (US 20170018237).
As per claim 1, Kim discloses a display device (Fig. 1, #1; [0052]) comprising:
a pixel (#PX; [0054]) comprising:
a light-emitting element (Fig. 2A, #ED; [0064]);
a first transistor (#T1) configured to control a driving current flowing through the light-emitting element (#ED), and including a gate connected to a first node (#N3), a first electrode connected to a second node (#N1), and a second electrode connected to a third node (#N2; [0066]);
a second transistor (#T2) configured to transmit a data voltage to a fourth node (#N4) in response to a first gate signal (#GW; [0067]);
a storage capacitor (#CST) connected between the first node (#N3) and the fourth node (#N4; [0076]);
an emission control transistor (#T9) configured to transmit a first power voltage (#ELVDD) to the second node (#N1) in response to a second gate signal or a first emission signal (#EM1), including a first gate which receives the first emission signal (#EM1), and the emission control transistor (#T9) being an oxide n-channel metal oxide semiconductor (NMOS) transistor ([0074]-[0075]); and
a third transistor (#T3) configured to connect the first node (#N3) and the third node (#N2) in response to the second gate signal (#GC), including a first gate configured to receive the second gate signal ([0068]).
However, Kim does not teach an emission control transistor configured to transmit a first power voltage to the second node in response to a second gate signal, including a second gate which receives the second gate signal.
Park teaches a control transistor (Fig. 3A, #SW1) including a second gate (#GE2) which receives the second gate signal ([0090]; [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the emission control transistor of Kim configured according to Park so as to provide a double-gate switching element that transmits a first power voltage to the second node in response to a second gate signal.
As per claims 2 and 17, Kim in view of Park discloses the display device (electronic apparatus) of claim 1 (claim 16), wherein the pixel further comprises:
a fourth transistor (Kim: #T4) configured to transmit a first initialization voltage to the first node (Kim: #N3) in response to a third gate signal (Kim: [0069]); and
a fifth transistor (Kim: #T5) configured to transmit a reference voltage to the fourth node (Kim: #N4) in response to the second gate signal (Kim: [0070]).
As per claims 4 and 19, Kim in view of Park discloses the display device (electronic apparatus) of claim 2 (claim 17), wherein the pixel further comprises:
a sixth transistor (Kim: #T6) configured to connect the third node (Kim: #N2) and an anode of the light-emitting element (Kim: #ED) in response to the first emission signal (Kim: [0071]; [0077]); and
a seventh transistor (Kim: #T7) configured to transmit a second initialization voltage to the anode of the light-emitting element (Kim: #ED) in response to a second emission signal (Kim: [0072]; [0077]).
As per claims 5 and 20, Kim in view of Park discloses the display device (electronic apparatus) of claim 4 (claim 19), wherein, in an emission period, the emission control transistor (Kim: #T9) configured to turn on in response to the first emission signal having an activation level, and a path of the driving current is formed through the emission control transistor (Kim: #T9), the first transistor (Kim: #T1), and the sixth transistor (Kim: #T6; [0066]; [0071]; [0074]).
As per claim 6, Kim in view of Park discloses the display device of claim 4, wherein each of the first to seventh transistors is an oxide NMOS transistor (Kim: [0075]).
As per claim 7, Kim in view of Park discloses the display device of claim 4, wherein the pixel further comprises:
a hold capacitor (Kim: #CHD) including a first electrode connected to the fourth node (Kim: #N4) and a second electrode configured to receive the first power voltage (Kim: [0076]).
As per claim 8, Kim in view of Park discloses the display device of claim 4, wherein the pixel further comprises:
a bias control transistor (Kim: #T8) configured to provide a bias voltage to the second node (Kim: #N1) in response to the second emission signal (Kim: [0073]).
As per claim 9, Kim in view of Park discloses the display device of claim 8, wherein the first transistor is a polysilicon p-channel metal oxide semiconductor (PMOS) transistor, and wherein each of the second to sixth transistors is an oxide NMOS transistor (Kim: [0075]).
As per claim 10, Kim in view of Park discloses the display device of claim 8, wherein each of the seventh transistor and the bias control transistor is a polysilicon PMOS transistor (Kim: [0075]).
As per claim 16, Kim discloses an electronic apparatus (Fig. 30, #200; [0190]) comprising:
a display device (Fig.1, #1; [0052]) comprising:
a pixel (#PX; [0054]); and
a processor (#210) configured to control the display device ([0191]-[0192]), the pixel comprising:
a light-emitting element (Fig. 2A, #ED; [0064]);
a first transistor (#T1) configured to control a driving current flowing through the light-emitting element (#ED), and including a gate connected to a first node (#N3), a first electrode connected to a second node (#N1), and a second electrode connected to a third node (#N2; [0066]);
a second transistor (#T2) configured to transmit a data voltage to a fourth node (#N4) in response to a first gate signal (#GW; [0067]);
a storage capacitor (#CST) connected between the first node (#N3) and the fourth node (#N4; [0076]);
an emission control transistor (#T9) configured to transmit a first power voltage (#ELVDD) to the second node (#N1) in response to a second gate signal or a first emission signal (#EM1), including a first gate which receives the first emission signal (#EM1), and the emission control transistor (#T9) being an oxide n-channel metal oxide semiconductor (NMOS) transistor ([0074]-[0075]); and
a third transistor (#T3) configured to connect the first node (#N3) and the third node (#N2) in response to the second gate signal, including a first gate configured to receive the second gate signal ([0068]).
However, Kim does not teach an emission control transistor configured to transmit a first power voltage to the second node in response to a second gate signal, including a second gate which receives the second gate signal.
Park teaches a control transistor (Fig. 3A, #SW1) including a second gate (#GE2) which receives the second gate signal ([0090]; [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the emission control transistor of Kim configured according to Park so as to provide a double-gate switching element that transmits a first power voltage to the second node in response to a second gate signal.
Allowable Subject Matter
Claims 3 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a display device comprising a pixel comprising a light-emitting element, a first transistor which controls a driving current flowing through the light-emitting element, a second transistor which transmits a data voltage to a fourth node in response to a first gate signal, a storage capacitor connected between the first node and the fourth node, and an emission control transistor configured to transmit a first power voltage to the second node in response to a second gate signal or a first emission signal, including a first gate which receives the first emission signal and a second gate which receives the second gate signal does not teach or fairly suggest in a compensation period, the emission control transistor is configured to turn on in response to the second gate signal having an activation level, and the first power voltage for which a threshold voltage of the first transistor is compensated is applied to the first node through the emission control transistor, the first transistor, and the third transistor.
Response to Arguments
Applicant's arguments filed 06/24/2026 have been fully considered but they are not persuasive.
Applicant states on page 12 in the Remarks, “Furthermore, one of ordinary skill in the art would not associate the first gate control voltage of Park with a specific one of the gate signals of Kim, let alone the compensation gate signal GC driving the third transistor T3”.
The Examiner, respectfully, does not agree. The prior art of Kim discloses in reference to Figures 1 and 2A, “The gate driver 20 may provide gate signals to the pixels PX. According to some embodiments, the gate signals may include a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, or the like” (Kim, paragraph 0055).
Kim discloses on Figure 2A, transistor T9, i.e., the emission control transistor, capable of transmitting the first power voltage ELVDD in response to the first emission control signal EM1.
Park discloses on Figure 3A, a control transistor SW1 including a second gate GE2 which receives the second gate signal (see Park paragraphs 0090 and 0093).
Therefore, the prior art of Kim in combination with Park would readily enable one of ordinary skill to have the emission control transistor of Kim when configured according to Park to provide a double-gate switching element to transmit the first power voltage to the second node in response to the second gate signal.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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