DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. OBJECTIONS TO THE CLAIMS
Claims 1-20 are objected to because of the following informalities:
As per claim 1-20, although applicant indicated that claims 21-43 will replace all prior version , and lists, of claims, it does not appear completely clear that claims 1-20 are being cancelled. Please clearly specify that claims 1-20 are cancelled.
Appropriate correction is required.
II. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 11,609,762. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the apparatus described in claim 21 of the instant application (19/061,779) are taught/suggested in claims 1-4 of the patented application (U.S. Patent No. 11,609,762). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12,236,242. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the apparatus described in claim 21 of the instant application (19/061,779) are taught/suggested in claims 1-4 of the patented application (U.S. Patent No. 12,236,242). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,809,869 in view of Ginzburg et al. (us pub.: 2013/0054899). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
As per claim 21, U.S. Patent No. 11,809,869 teaches/suggests an apparatus comprising: a processor, the processor to perform operations corresponding to an instruction, the instruction identifying a first two-dimensional source matrix in a first storage, the operations including to: load elements from element positions of each row of the first two-dimensional source matrix in the first storage into corresponding element positions of a first two-dimensional destination matrix in a second storage; and load elements from element positions of each row of a second two-dimensional source matrix in the first storage into corresponding element positions of a second two-dimensional destination matrix in the second storage when an indicator indicates that the second two-dimensional source matrix is to be loaded (Claim 1).
U.S. Patent No. 11,809,869 does not teaches the apparatus comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
being coupled to the plurality of memory controllers, and coupled to the L2 cache memory having a plurality of cores to perform operations.
Ginzburg teaches/suggests an apparatus comprising: a plurality of memory controllers (e.g. it would have been obvious to one of ordinary skilled in the art to duplicate MCH (130) in Fig. 1); a level-two (L2) cache memory coupled to the plurality of memory controllers ([0021]); and being coupled to the plurality of memory controllers, and coupled to the L2 cache memory, having a plurality of cores to perform operations (Fig. 1-2; and [0013]-[0041]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Ginzburg’s matrix operations into U.S. Patent No. 11,809,869’s apparatus to obtain the invention as specified in claim 21.
III. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-43 are rejected under 35 U.S.C. 103 as being unpatentable over Gilbert et al. (US Patent 5,781,779) in view of Ginzburg et al. (us pub.: 2013/0054899).
As per claim 21, Gilbert teaches/suggests an apparatus comprising: processor to perform operations (e.g. associated with computer would obviously have corresponding processor for executing corresponding program: Fig. 1; col. 2, ll. 46-57), identifying a two-dimensional source matrix, the operations including to: load elements from the two-dimensional source matrix into a two-dimensional destination matrix (e.g. associated with copying from source matrix into destination matrix: col. 10, ll. 59-62); and load elements from a two-dimensional source matrix into a two-dimensional destination matrix when an indicator indicates that the two-dimensional source matrix is to be loaded (e.g. associated with copying from source matrix into destination matrix: col. 10, ll. 59-62) (Fig. 1; col. 2, ll. 46-57; and col. 10, ll. 59-62).
Gilbert does not teach the apparatus comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
being coupled to the plurality of memory controllers, and coupled to the L2 cache memory, having a plurality of cores to perform operations corresponding to an instruction, the instruction identifying a first two-dimensional source matrix in a first storage, the operations including to:
operating with element positions of each row of the first two-dimensional matrix in the first storage into corresponding element positions of a first two-dimensional matrix in a second storage; and
operating with element positions of each row of a second two-dimensional matrix in the first storage into corresponding element positions of a second two-dimensional matrix in the second storage as the second two-dimensional matrix is operated upon.
Ginzburg teaches/suggests an apparatus comprising: a plurality of memory controllers (e.g. it would have been obvious to one of ordinary skilled in the art to duplicate MCH (130) in Fig. 1); a level-two (L2) cache memory coupled to the plurality of memory controllers ([0021]); and being coupled to the plurality of memory controllers, and coupled to the L2 cache memory, having a plurality of cores to perform operations corresponding to an instruction, the instruction identifying a first two-dimensional source matrix in a first storage ([0021]-[0034]), the operations including to: operating with element positions of each row of the first two-dimensional matrix in the first storage into corresponding element positions of a first two-dimensional matrix in a second storage (e.g. associated with having a first one of window 204/208 being stored as window 254/258 in Fig. 2: [0035]); and operating with element positions of each row of a second two-dimensional matrix in the first storage into corresponding element positions of a second two-dimensional matrix in the second storage as the second two-dimensional matrix is operated upon (e.g. associated with having a second one of window 204/208 being stored as window 254/258 in Fig. 2: [0035]) (Fig. 1-2; and [0013]-[0041]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Ginzburg’s matrix operations into Gilbert’s apparatus for the benefit of implementing low latency operations (Ginzburg, [0015]) to obtain the invention as specified in claim 21.
As per claim 22, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the first two-dimensional source matrix and the second two-dimensional source matrix are stored next to one another in the first storage (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]).
As per claim 23, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the first or second storage comprises a plurality of registers of the processor (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]).
As per claim 24, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the first or second storage comprises non-register storage of the processor for use in tile operations (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]).
As per claim 25, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the first and second two-dimensional source matrices each have eight rows and sixteen columns (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 26, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the plurality of cores include graphics cores (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 27, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the processor includes heterogeneous graphics cores (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 28, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus further comprising an instruction converter to convert the instruction into one or more instructions of a different instruction set executable by the plurality of cores (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 29, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the plurality of cores are to perform operations corresponding to an instruction to configure a number of columns of the first storage or the second storage (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 30, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein a core of the plurality of cores is to stop performing the operations corresponding to the instruction due to an event and then restart after the event (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 31, Gilbert and Ginzburg teach/suggest all the claimed features of claim 21 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the first two-dimensional source matrix and the second two-dimensional source matrix are stored next to one another in the first storage, wherein the first and second two-dimensional source matrices each have eight rows and sixteen columns, wherein the plurality of cores include graphics cores, and wherein the plurality of cores are to perform operations corresponding to an instruction to configure a number of columns of the first storage or the second storage (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 32, claim 32 is rejected in accordance to the same rational and reasoning as the above rejection of claim 21, where Gilbert and Ginzburg further teach/suggest the apparatus comprising: convert circuitry to convert a first instruction into one or more other instructions (e.g. associated with instruction being decoded) (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041])
As per claims 33-35, claims 33-35 are rejected in accordance to the same rational and reasoning as the above rejection of claims 22, 25, and 26.
As per claim 36, Gilbert and Ginzburg teach/suggest all the claimed features of claim 32 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the convert circuitry is to convert a second instruction into one or more other instructions, and further comprising second execution circuitry to perform operations corresponding to the one or more other instructions converted from the second instruction, including to configure a number of columns of the first storage or the second storage (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 37, claim 37 is rejected in accordance to the same rational and reasoning as the above rejection of claims 21 and 32, where Gilbert and Ginzburg further teach/suggest the apparatus comprising: an instruction converter (e.g. associated with instruction decoder) (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041])
As per claims 38-39, claims 38-39 are rejected in accordance to the same rational and reasoning as the above rejection of claims 22, 25 and 26
As per claim 40, Gilbert and Ginzburg teach/suggest all the claimed features of claim 37 above, where Gilbert and Ginzburg further teach/suggest the apparatus comprising wherein the instruction converter comprises a machine-readable storage medium storing code that when executed by the apparatus causes the apparatus to said convert the first instruction into the one or more other instructions (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 41, claim 41 is rejected in accordance to the same rational and reasoning as the above rejection of claims 21, 32, and 37, where Gilbert and Ginzburg further teach/suggest the non-transitory machine-readable storage medium storing instructions that, when executed by a machine, cause the machine to perform operations, including to: receive an instruction (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041])
As per claims 42, claims 42 are rejected in accordance to the same rational and reasoning as the above rejection of claims 22.
As per claim 43, Gilbert and Ginzburg teach/suggest all the claimed features of claim 41 above, where Gilbert and Ginzburg further teach/suggest the non-transitory machine-readable storage medium comprising wherein the operations include to receive a second instruction and perform operations corresponding to the second instruction to configure a number of columns of the first storage or the second storage (Gilbert, Fig. 1; col. 2, ll. 46-57; col. 10, ll. 59-62; and Ginzburg, Fig. 1-2; [0013]-[0041]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
IV. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 21-43 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 July 10, 2026
Prosecution Insights