DETAILED ACTION
This is in response to the application filed on February 25, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1 and 11 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/2/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 – 10 are objected to because of the following informalities: independent claim 1 states “a function interface that provides a connection between the intra-processor network and functional unit of the processor.” The examiner suggests amending claim 1 so state “a function interface that provides a connection between the intra-processor network and a functional unit of the processor.” Claims 2 – 10 inherit this objection based on their dependencies. Appropriate correction is required.
Claims 1 – 10 are objected to because of the following informalities: independent claim 1 ends with two scenarios. The first scenario is “in response to the target processor identifier being equal to the first identifier.” The second scenario is “in response to the target processor identifier not being different than the first identifier.” This phrase of “not being different than” is logically equivalent to the prior phrase of “being equal.” The examiner recommends amending the last limitation of claim 1 to state “in response to the target processor identifier equal to. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 11 of U.S. Patent No. 12,271,333. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claims are broader than the claims of 12,271,333.
12,271,333
19/062301
1. A reconfigurable dataflow unit (RDU) comprising:
an intra-RDU network; a first interface circuit coupled between the intra-RDU network and a first external interconnect external to the RDU, wherein the RDU is a first RDU;
a second interface circuit coupled between the intra-RDU network and a second external interconnect external to the first RDU; a third interface circuit coupled between the intra-RDU network and a third external interconnect external to the first RDU;
an array of configurable units having a coarse grain reconfigurable architecture and including a plurality of configurable processing units and a plurality of configurable memory units connected by an array level network;
one or more function interfaces that respectively provide a connection between the intra-RDU network and the array level network or another functional unit of the first RDU;
an identity register to store a first identifier for the first RDU; and
a pass-through table to store an interface circuit identifier for each of a plurality of other RDU identifiers, the interface circuit identifier capable of identifying one of at least the second interface circuit and the third interface circuit;
the first interface circuit comprising: receiving circuitry to receive a first packet from the first external interconnect and extract a target RDU identifier from the first packet;
a comparator to compare the target RDU identifier to the first identifier;
target RDU circuitry to communicate over the intra-RDU network to a function interface of the one or more function interfaces based on information in the first packet in response to a determination by the comparator that the target RDU identifier is equal to the first identifier; and
pass-through RDU circuitry to access the pass-through table and retrieve the interface circuit identifier for the target RDU identifier and, in response to a determination by the comparator that the target RDU identifier is not equal to the first identifier, send the target RDU identifier and other information from the first packet to the second interface circuit over the intra-RDU network, wherein the interface circuit identifier for the target RDU identifier is equal to an identifier for the second interface circuit.
1. A processor comprising:
an intra-processor network;
a plurality of interface circuits, including a first interface circuit and a target interface circuit, coupled between the intra-processor network and a respective one of a plurality of external interconnects, including a first external interconnect, external to the processor;
a function interface that provides a connection between the intra-processor network and functional unit of the processor;
an identity register to store a first identifier for the processor; and
a pass-through table to store a plurality of interface circuit identifiers respectively corresponding to a plurality of other processor identifiers;
the first interface circuit comprising: receiving circuitry to extract a target processor identifier from a first packet received through a first external interconnect;
target processor circuitry that, in response to the target processor identifier being equal to the first identifier, communicates over the intra-processor network to the function interface based on information in the first packet; and
pass-through processor circuitry that, in response to the target processor identifier not being different than the first identifier, retrieves a target interface circuit identifier corresponding to the target processor identifier from the pass-through table and sends the target processor identifier and other information from the first packet to the target interface circuit identified by the target interface circuit identifier over the intra-processor network.
2. The RDU of claim 1, wherein the RDU is implemented on a single integrated circuit die, or the RDU comprises two or more integrated circuit dies mounted in a multi-die package.
3. The RDU of claim 1, the second interface circuit comprising forwarding circuitry to receive the target RDU identifier and the other information from the first packet over the intra-RDU network, create a second packet based on the target RDU identifier and other information from the first packet, and send the second packet over the second external interconnect.
4. The RDU of claim 3, wherein the second external interconnect is coupled to a second RDU, the forwarding circuitry further comprising
circuitry to determine an address for the second RDU and to use the address for the second RDU to send the second packet to the second RDU over the second external interconnect.
5. The RDU of claim 4, wherein the circuitry to determine an address for the second RDU comprises a base address register table to provide addresses for a plurality of other RDUs, including the second RDU.
6. The RDU of claim 4, wherein the circuitry to determine an address for the second RDU comprises a register to hold the address for the second RDU.
7. The RDU of claim 1, wherein the function interface comprises a memory interface circuit coupled between the intra-RDU network and an external memory bus; wherein the memory interface circuit is identified for communication over the intra-RDU network based on a memory address provided with the first packet.
8. The RDU of claim 1, wherein the function interface comprises an array interface circuit coupled between the intra-RDU network and the array level network of the array of configurable units; wherein the array interface circuit is identified for communication over the intra-RDU network based on an identifier of the array interface circuit provided in the first packet.
9. The RDU of claim 1, the first interface circuit further comprising a hung array bit to indicate that communication with the array of configurable units over the intra-RDU network should be suppressed; the target RDU circuitry further comprising circuitry to evaluate the hung array bit and in response to the hung array bit being set with the target RDU identifier equal to the first identifier and the function interface being an identifier for an array interface in the array of configurable units, sending a response to the first packet back on the first external interconnect without communicating over the intra-RDU network.
10. The RDU of claim 1, the first packet also including a transaction type with the first interface circuit capable to recognize transaction types of: a stream write to a first configurable memory unit in the array of configurable units; a stream clear to send (SCTS) to a second configurable memory unit in the array of configurable units; a remote write to a memory controller of the RDU; a remote read request to the memory controller of the RDU; a remote read completion to a third configurable memory unit in the array of configurable units; a barrier request; and a barrier completion to a fourth configurable memory unit in the array of configurable units.
2. The processor of claim 1, wherein the processor is implemented on a single integrated circuit die, or the processor comprises two or more integrated circuit dies mounted in a multi-die package.
3. The processor of claim 1, further comprising forwarding circuitry in the target interface circuit to receive the target processor identifier and the other information from the first packet over the intra-processor network, create a second packet based on the target processor identifier and other information from the first packet, and send the second packet over a second external interconnect of the plurality of external interconnects.
4. The processor of claim 3, the forwarding circuitry further comprising
circuitry to determine an address for a second processor and to use the address for the second processor to send the second packet to the second processor over the second external interconnect.
5. The processor of claim 4, the circuitry to determine an address for the second processor comprises a base address register table to provide addresses for a plurality of other processors, including the second processor.
6. The processor of claim 4, wherein the circuitry in the forwarding circuitry to determine an address for the second processor comprises a register to hold the address for the second processor.
7. The processor of claim 1, the function interface comprising a memory interface circuit coupled between the intra-processor network and an external memory bus, wherein the memory interface circuit is identified for communication over the intra-processor network based on a memory address provided with the first packet.
8. The processor of claim 1, further comprising: an array of configurable units coupled together with an array level network, wherein the processor has a coarse-grained reconfigurable architecture; and an array interface circuit coupled between the intra-processor network and the array level network, wherein the function interface comprises the array interface circuit; wherein the array interface circuit is identified for communication over the intra-processor network based on an identifier of the array interface circuit provided in the first packet.
9. The processor of claim 8, the first interface circuit further comprising a hung array bit to indicate that communication with the array of configurable units over the intra-processor network should be suppressed; the target processor circuitry further comprising circuitry to evaluate the hung array bit and in response to the hung array bit being set with the target processor identifier equal to the first identifier and the identifier of the array interface circuit being provided in the first packet, sending a response to the first packet back on the first external interconnect without communicating over the intra-processor network.
10. The processor of claim 8, further comprising a memory controller, the first interface circuit capable to recognize a transaction type included in the first packet, including transaction types of: a stream write to a first configurable memory unit in the array of configurable units; a stream clear to send (SCTS) to a second configurable memory unit in the array of configurable units; a remote write to the memory controller; a remote read request to the memory controller; a remote read completion to a third configurable memory unit in the array of configurable units; a barrier request; and a barrier completion to a fourth configurable memory unit in the array of configurable units.
11. A method for routing packets in a computing system that includes three or more reconfigurable dataflow units (RDUs) each having a coarse grain reconfigurable architecture, the method comprising:
receiving, over a first external interconnect at a first interface circuit of a first RDU of the three or more RDUs, a first packet;
extracting a target RDU identifier from the first packet;
determining whether the target RDU identifier identifies the first RDU;
in response to determining that the target RDU identifier identifies the first RDU, communicating over a switching array fabric of the first RDU to a function interface of the first RDU identified in the first packet to perform a transaction indicated by the first packet; and
in response to determining that the target RDU identifier does not identify the first RDU, accessing a pass-through table to retrieve an interface circuit identifier for the target RDU identifier that identifies a second interface of the first RDU coupled to a second external interconnect that is also coupled to a second RDU of the three or more RDUs, and sending the target RDU identifier and other information from the first packet to the second interface over the switching array fabric of the first RDU.
11. A method for routing packets in a computing system that includes a plurality of processors, the method comprising:
receiving, over a first external interconnect at a first interface circuit of a first processor of the plurality of processors, a first packet that includes a target processor identifier;
determining whether the target processor identifier identifies the first processor;
in response to determining that the target processor identifier identifies the first processor, communicating over an intra-processor network of the first processor to a function interface of the first processor identified in the first packet to perform a transaction indicated by the first packet; and
in response to determining that the target processor identifier does not identify the first processor, retrieving a target interface circuit identifier from a pass-through table based on the target processor identifier and sending the target processor identifier and other information from the first packet to a second interface circuit identified by the target interface circuit identifier over the intra-processor network.
Allowable Subject Matter
Claims 1 – 20 contain allowable subject matter.
The following is an examiner’s statement of reasons for indicating allowable subject matter: The primary reason for the indication of allowable subject matter of the claims in this application is the inclusion of the specific details of a system including a plurality of processors, receiving a first packet with a target processor identifier at a first processor’s interface circuit connected to an external interconnect, determining whether the target processor identifier identifies the first processor, if the target processor identifier identifies the first processor: communicating over an intra-processor network of the first processor to a function interface of the first processor to perform a transaction indicated by the first packet, and if the target processor identifier does not identify the first processor: retrieving a target interface circuit identifier from a pass-through table and sending the target processor identifier and other information from the first packet to a second interface circuit identified over the intra-processor network, as are now included in all of the independent claims, in combination with the other elements recited, which is not found in the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 2023/0058989 teaches a SoC with an interconnect fabric, cores, memory controller, and an off-chip interconnect, as well as using routing tables.
U.S. Patent 6543406 teaches receiving packets and determining whether the packet is for interprocessor or intraprocessor communication, the packet identifying a destination processor P.
U.S. Patent 12,271,333 is the granted patent to the parent application.
U.S. Patent 10,698,853 teaches a reconfigurable data processor with external interconnect, top level network, AGCUs, packets with destination identifiers, and a mapping table.
U.S. Patent Application 20150117458 and Patent 9787586 teach forwarding tables for routing.
U.S. Patent 7606229 teaches comparing an address/ID to a register value.
‘SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts; by Prabhakar et al. teaches flow IDs in switch flow tables for Reconfigurable Dataflow Network (RDN) traffic, a top level network (TLN), memory interfaces, die-to-die interfaces, etc.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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