Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on or before 2025-02-25 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Drawings
The drawings are objected to because of the following informalities:
Figure 6 labels the pixel array as “PARRY of AR” but the specification, in paragraph [0055], refers to this component as “PARRAY of AR”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The description of the connections of the resistors R7’-R9’ in Paragraph [0068] does not match the connections as shown in Figure 6. The connections in Figure 6 require each of the resistors R7’-R9’ to be connected to node N5’.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 states “the other upper partial edge region” in lines 8-9. There is insufficient antecedent basis for this in the claim. For the purposes of compact prosecution, the examiner will interpret this to read – an other upper partial edge region --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyou et al. (US-20230206795-A1).
Regarding Claim 1, Lyou teaches a display device comprising:
a display panel (Fig 8 in its entirety) including an edge region (Refer to annotated Figure 8 of Lyou);
a loop resistance circuit disposed in the edge region of the display panel (Fig 8: plurality of resistors comprised of branches 161L/162L (additionally labeled RL) on the left side and 161R/162R (additionally labeled RR) on the right side); and
a crack detection circuit (Fig 11: tester contained with flexible circuit board, 170) configured to detect a resistance value of the loop resistance circuit (Para [0084] teaches measuring a resistance value),
wherein the loop resistance circuit includes first detection regions and second detection regions (Refer to annotated Figure 8 of Lyou),
wherein the edge region is divided into a first edge region including a right edge region and an upper partial edge region and a second edge region including a left edge region and the other upper partial edge region (Can be seen in Fig 8, both detection regions contain a left/right side and a partial upper side),
wherein the first detection regions correspond to the first edge region, and wherein the second detection regions correspond to the second edge region (Refer to annotated Fig 8 of Lyou).
Regarding Claim 2, Lyou teaches the display device of claim 1, wherein the first detection regions and the second detection regions are axisymmetric with each other (Can be seen in the Fig 8 of Lyou).
Regarding Claim 3, Lyou teaches the display device of claim 2, wherein the first detection regions and the second detection regions, which are axisymmetric with each other, have the same resistance value (Para [0063] and [0071] teach that the first and second detection regions, RL & RR, may be disposed in such a way that a specific resistance value is achieved (for example one kilo ohm), it further teaches that the values of the resistors are not limited. This suggests the values of RL & RR may be the same).
PNG
media_image1.png
758
584
media_image1.png
Greyscale
Annotated Fig 8 of Lyou
Regarding Claim 5, Lyou teaches the display device of claim 1, wherein the first detection regions comprise a plurality of first resistors electrically connected to each other and configured to have different resistance values (Para [0063] and [0071] teach the resistors of the detection regions are not limited to having the same resistance),
wherein the second detection regions comprise a plurality of second resistors electrically connected to each other and configured to have different resistance values (Para [0063] and [0071] teach the resistors of the detection regions are not limited to having the same resistance), and
wherein the plurality of first resistors and the plurality of second resistors are electrically disconnected from one another (Fig 8 shows the plurality of resistors on the left side, RL, electrically disconnected from the plurality of resistors on the right side, RR).
Regarding Claim 9, Lyou teaches the display device of claim 5, wherein the plurality of first resistors (unlabeled but can be seen in Figure 8, RL for example) is corresponding to different detection regions of the first detection regions (Para [0063] teaches wiring the first resistors in series-parallel so that a location of the crack is easily identifiable, therefore different detection regions are required to determine the location), and the plurality of second resistors (unlabeled but can be seen in Figure 8, RR for example) are corresponding to different detection regions of the second detection regions (Para [0071] teaches wiring the second resistors in series-parallel so that a location of the crack is easily identifiable, therefore different detection regions are required to determine the location).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability should not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lyou.
Regarding Claim 4, Lyou does not explicitly teach wherein the first detection regions and the second detection regions, which are axisymmetric with each other, have different resistance values. However, Para [0063] and [0071] of Lyou does teach that the first and second detection regions, RL & RR, may be disposed in such a way that a specific resistance value is achieved, it further teaches that the values of the resistors are not limited. This suggests the values of RL & RR may be different. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lyou, to adjust the values of the resistors such that the first and second detection regions have different resistance values. A motivation for this modification would be to design the resistance values required by other circuit constraints such as voltage, current or space available.
Claim 6, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lyou in view of Sunghae et al. (KR-20240025457-A. Refer to attached machine translation for references cited).
Regarding Claim 6, Lyou teaches the first detection regions comprise a plurality of first resistors (Can be seen in Fig 8, RL for example), and wherein the second detection regions comprise a plurality of second resistors (Can be seen in Fig 8, RR for example). Lyou does not teach the resistors being electrically disconnected from one another and configured to have different resistance values. However, Sunghae teaches resistors electrically disconnected from one another and configured to have different resistance values (Fig 8 shows resistors R1 and R2 electrically disconnected from one another and Para [0072] teaches that an output may be generated with different values according to the resistance values of R1 and R2, therefore these resistance values may be different). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Lyou to electrically disconnect the resistors from each other. A motivation for this modification is so that each area of the circuit may have its own output signal associated with it as taught by Sunghae in para [0060].
Regarding Claim 8, Lyou does not explicitly teach wherein the crack detection circuit comprises:
an integrator configured to supply a detection driving voltage to the loop resistance circuit and perform an integral on a signal fed back from the loop resistance circuit;
a comparator configured to compare an integrator output voltage with a reference voltage to generate a comparator output; and
a counter configured to count a time, taken until a logic level of the comparator output is inverted, and output a count value as a resistance value of the loop resistance circuit.
However, Sunghae teaches wherein the crack detection circuit comprises:
an integrator (Fig 3: integrator, 241) configured to supply a detection driving voltage to the loop resistance circuit and perform an integral on a signal fed back from the loop resistance circuit (Para [0064] teaches using an integrator to control the detection intervals for the crack detection circuits);
a comparator (Fig 3: comparator, 242) configured to compare an integrator output voltage (Fig 3: INT_OUT) with a reference voltage (Fig 3: REF_TOP) to generate a comparator output (Fig 3: D_CMP_O); and
a counter (Fig 3: level shifter & code generator, 243 & 244) configured to count a time, taken until a logic level of the comparator output is inverted, and output a count value as a resistance value of the loop resistance circuit (Para [0070]-[0072] teaches counting to determine the rising time of the comparator output and output a signal according to the resistance values of R1 and R2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the display device of Lyou to include the integrator, comparator and counter of Sunghae. A motivation for this modification is that the integrator, comparator and counter allow for multiple values of resistance by being able to determine between multiple resistance values, as taught by Sunghae in para [0063].
Regarding Claim 10, Lyou further teaches wherein the plurality of first resistors (unlabeled but can be seen in Figure 8, RL for example) is corresponding to different detection regions of the first detection regions (Para [0063] teaches wiring the first resistors in series-parallel so that a location of the crack is easily identifiable, therefore different detection regions are required to determine the location), and the plurality of second resistors (unlabeled but can be seen in Figure 8, RR for example) are corresponding to different detection regions of the second detection regions (Para [0071] teaches wiring the second resistors in series-parallel so that a location of the crack is easily identifiable, therefore different detection regions are required to determine the location).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lyou in view of Zuo et al. (CN-111223429-B. Refer to attached machine translation for references cited).
Regarding Claim 7, Lyou teaches wherein the first detection regions comprise a plurality of first resistors electrically connected to each other and configured to have different resistance values (Para [0063] and [0071] teach the resistors of the detection regions are not limited to having the same resistance),
wherein the second detection regions comprise a plurality of second resistors electrically connected to each other and configured to have different resistance values (Para [0063] and [0071] teach the resistors of the detection regions are not limited to having the same resistance).
Lyou does not teach wherein the plurality of first resistors and the plurality of second resistors are electrically connected to each other through a third resistor. However, Zuo teaches wherein the plurality of first resistors and the plurality of second resistors are electrically connected to each other through a third resistor (Fig 1: bridge resistor, R01). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the crack detection circuit of Lyou to incorporate the third resistor of Zuo. A motivation for this modification is to use the bridge resistor to separate out sub-regions as taught by Zuo in Para [0041].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M, T, Th, F 10:30-17:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEREMIAH J BARRON/Examiner, Art Unit 2858
/DANIEL R MILLER/Primary Examiner, Art Unit 2858
Prosecution Insights