DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 2 and 14 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: a second memory coupled to the controller ,wherein the controller comprises: a first memory unit, wherein a value in the first memory unit represents whether input data in a current respective storage area needs to be refreshed; and a second memory unit, wherein a value in the second memory unit represents whether there is input data in the process of executing the program to be refreshed to the respective storage area; or wherein the controller comprises: a third memory unit, wherein a value in the third memory unit represents whether output data currently refreshed to the respective storage area needs to be stored to the second memory; and a fourth memory unit, wherein a value in the fourth memory unit represents whether there is output data in the process of executing the program to be stored to the second memory; and in regard to claim 14, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: the computational storage system further comprises a second memory coupled to the controller, and the controller comprises: a first memory unit, wherein a value in the first memory unit represents whether input data in a current respective storage area needs to be refreshed; Anda second memory unit, wherein a value in the second memory unit represents whether there is input data in the process of executing the program to be refreshed to the respective storage area; or the controller comprises: a third memory unit, wherein a value in the third memory unit represents whether output data currently refreshed to the respective storage area needs to be stored to the second memory; Anda fourth memory unit, wherein a value in the fourth memory unit represents whether there is output data in the process of executing the program to be stored to the second memory.
Claim(s) 3-9, 11 and 15-19 depend from claim(s) 2 and 14 and as such are also objected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10, 12-13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20230185740 to Nguyen et al. (“Nguyen”) in view of U.S. Patent/Publication No. 20250217931 to Kadu et al. (“Kadu”).
As to claim 1, Nguyen teaches substantially the claimed invention, including, but not limited to: A computational storage system (As found in at least FIG. 3: 135), comprising: a computing processing component configured to execute a program (As found in at least FIG. 3: 305; also see at least [0035]: “Circuit 305 may be considered the processing heart of accelerator 135, and may perform execution of the various models. To that end, circuit 305 may include cores 320-1 through 320-3 (which may be referred to collectively as cores 320). Cores 320 may be portions of circuit 305 that may execute various instructions, similar to cores in processors and GPUs currently in use. Each core 320 may execute a kernel of an operating system and an application on top of that kernel: the applications may execute the models.”); a first memory comprising a respective storage area configured for input data/output data in a process of executing the program by the computing processing component (As found in at least FIG. 3: 310; further, also see at least [0036]: “First tier storage 310 and second tier storage 315 may be different storage options within accelerator 135. For example, first tier storage 310 may be a form of memory, similar to memory 115, and may be implemented using DRAM or SRAM, among other options. When first tier storage 310 is implemented as a form of memory, accelerator 135 may include memory controller 325 to manage writing data to first tier storage 310 and reading data from first tier storage 310”); and a controller coupled to the first memory and configured to: refresh the input data/output data in the process of executing the program into the respective storage area in batches sequentially, wherein a size of the input data/output data in the process of executing the program is greater than a capacity size of the respective storage area (As found in at least FIGS. 3-4; and further as found in at least [0055]: “Prefetcher 335 may identify batches 410 to be used in executing models 405 by circuit 305 of FIG. 3. For example, prefetcher 335 may know that batches 410 may be used in order, and that only one batch 410 of data may be needed for each model 405 for part of a given execution. Thus, rather than storing an entire model 405 in first tier storage 310, individual batches 410 of models 405 may be stored in first tier storage 310, with later batches 410 fetched when needed”).
While Nguyen may not expressly teach refresh the input/output data, memory refreshing operations are well-known and well-understood; memory here refers to all storage locations that may be operable to store input/output data; for example, temporary memory location, buffers, registers, etc.
Thus, relevantly and complementarily, Kadu teaches in at least [0031]: For example, when the content preparation 201 refreshes data stored in the frame buffer 203, the content preparation 201 sends a trigger 209 to the graphic automation framework 207 to indicate that the data stored in the frame buffer has been refreshed.
Nguyen and Kadu are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: refreshing data operations in memory that may include buffering, batching.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Nguyen as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Kadu also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: there is nothing new in an operation that refreshes stored data, whether the storage location is an array, a buffer, a register, etc. The benefits of data refresh are well-known: these locations can be implemented using fast-operating memory types such as SRAM or DRAM; yet, these memory types require data refreshing.
Therefore, it would have been obvious to combine Nguyen with Kadu to make the above modification.
As to claim 10, Nguyen teaches wherein the computing processing component is configured to: load the program to be executed; and read input data refreshed to the respective storage area; or refresh output data obtained after the program has processed the input data into the respective storage area (As found in at least, as claimed in the alternative, FIG. 3 and [0046]: 305 executes models when data is loaded).
As to claim 12, Nguyen teaches the computational storage system supports simultaneous execution of a plurality of programs, the first memory comprises a corresponding storage area respectively configured for input data/output data in a process of executing each of the plurality of programs, and the controller is configured to: configure a corresponding memory unit for a storage area corresponding to each of the plurality of programs respectively, and configure a corresponding memory unit for each of the plurality of programs (As found in at least FIG. 3: storage system comprises at least portions 310 and 315, as found in at least [0043] these storage portions expedite execution of programs).
As to claim 13, see rejection to at least claim 1; moreover, at least Nguyen teaches a host configured to send a first command, as found in at least FIG. 3: 110.
As to claim 20, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights