DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 3, 4 5, 6, 7, 8, 11, 12, 13, 14, 15 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over respective claims ‘1 & 12’, 1, 5, 6, 7, 8, 9, 10, ‘14 & 18’, 14, 16, 17, 18 and ‘14 & 19’ of U.S. Patent No. 12,265,411 (U.S. App. 18/410,523). Although the claims at issue are not identical, they are not patentably distinct from each other because, as follows,
Regarding independent claim 1, US Pat 12,265,411 teaches a Low-Dropout voltage regulator (LDO) comprising:
an amplifier supplied with a voltage reference (VREFM), the amplifier configured to produce a source current to or a sinking current from a load; a decoupling capacitor, connected to an output of the amplifier, and configured to decouple a high-edge ground (HGND) from a power source; a power down control unit (PDCTRL) configured to maintain the HGND in an active mode of the amplifier and in a power-down mode of the amplifier (a Low-dropout voltage regulator (LDO)… and in a power-down mode of the amplifier; claim 1, L1-7); and
a VREFGEN circuit configured to supply the VREFM to the amplifier, the VREFGEN circuit configured to transform the core power voltage into a current through a diode-connected MOSFET and a resistor in series and supply a difference between an IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM (a VREFGEN circuit…to the amplifier as the VREFM; claim 12).
Regarding independent claim 11, US Pat 12,265,411 teaches a Low-Dropout voltage regulator (LDO) comprising (LDO; claim 14, L1):
an amplifier configured to produce a source current to or a sinking current from a load; a Voltage Reference Generator (VREFGEN) circuit connected to a first input of the amplifier and configured to track a fixed voltage reference (VREF) and supply a voltage reference output (VREFM) to the amplifier; a decoupling capacitor, connected to an output of the amplifier and configured to decouple a high-edge ground (HGND) from a power source; and a Power Down Control Unit (PDCTRL) configured to maintain the HGND in an active mode of the amplifier and in a power-down mode of the amplifier (a Low-dropout voltage regulator (LDO)… and in a power-down mode of the amplifier; claim 14 L2-9),
wherein the VREFGEN circuit is configured to receive the VREF and to determine a difference between a core power voltage and an Input/Output (IO) power voltage to supply the VREFM to the amplifier (wherein the VREFGEN circuit … to the amplifier; claim 18).
Regarding independent claim 17, US Pat 12,265,411 teaches a Low-Dropout voltage regulator (LDO) (LDO; claim 14, L1) comprising:
an amplifier configured to produce a source current to or a sinking current from a load; a Voltage Reference Generator (VREFGEN) circuit connected to an input of the amplifier and configured to track a fixed voltage reference (VREF) and supply a voltage reference output (VREFM) to the amplifier; a decoupling capacitor, connected to an output of the amplifier and configured to decouple a high-edge ground (HGND) from a power source; and a Power Down Control Unit (PDCTRL) configured to maintain the HGND in an active mode of the amplifier and in a power-down mode of the amplifier (a Low-dropout voltage regulator (LDO)… and in a power-down mode of the amplifier; claim 14 L2-9),
wherein the VREFGEN circuit is configured to transform the core power voltage into a first current that flows through a first diode connected MOSFET and a first resistor in series and configured to generate a second current that corresponds to the first current and flows through a second diode connected MOSFET and a second resistor from an IO power voltage to supply the VREFM to the amplifier (wherein the VREFGEN circuit … to the amplifier; claim 19).
Regarding claim 2, US Pat 12,265,411 teaches wherein the PDCTRL includes a resistor connected at one end of the resistor to a core power voltage through a first switch and connected at another end of the resistor to the output of the amplifier, an input of the amplifier, and to a first diode-connected Metal Oxide Semiconductor Field Effect Transistor (MOSFET) connected in series to a second diode-connected MOSFET that is coupled to ground through a second switch (wherein the PDCTRL includes… coupled to ground through a second switch; claim 1, L7-10).
Regarding claim 3, US Pat 12,265,411 teaches at least one of the first diode-connected MOSFET and the second diode-connected MOSFET is a PMOS diode-connected MOSFET (claim 5).
Regarding claim 4, US Pat 12,265,411 teaches at least one of the first diode-connected MOSFET and the second diode-connected MOSFET is an NMOS diode-connected MOSFET (claim 6).
Regarding claims 5, US Pat 12,265,411 teaches the decoupling capacitor includes a first capacitor and a second capacitor attached with the load, wherein the first capacitor is a pure Metal-Oxide-Metal (MOM) capacitor (CMOM) connected at one end to the output of the amplifier and at another end to ground, and the second capacitor is a core P-type Metal Oxide Semiconductor Capacitor (PMOSCAP) connected at one end to the output of the amplifier and at another end to the core power voltage or to an Input/Output (IO) power voltage (claim 7).
Regarding claims 6, US Pat 12,265,411 teaches one or more MOSFETs is placed beneath the CMOM to get a highest capacitance density (claim 8).
Regarding claim 7, US Pat 12,265,411 teaches the amplifier includes a push-pull amplifier that has a push PMOS to the load and a pull NMOS from the load, wherein the push PMOS and the pull NMOS share a drain to connect with the load (claim 9).
Regarding claim 8, US Pat 12,265,411 teaches a gate bias of the push PMOS and the pull NMOS is controlled by a single amplifier or a dual amplifier (claim 10).
Regarding claims 9, US Pat 12,265,411 teaches the VREFGEN circuit is configured to receive a fixed voltage reference and selectively supply the fixed voltage reference to the amplifier as the VREFM (claim 11).
Regarding claim 10, US Pat 12,265,411 teaches the VREFM is directly forced by an input voltage or directly forced through the VREFGEN circuit that is configured to transfer a difference between the core power voltage and an IO power voltage (claim 13).
Regarding claim 12, US Pat 12,265,411 teaches wherein the PDCTRL includes a resistor connected at one end of the resistor to a core power voltage through a first switch and connected at another end of the resistor to the output of the amplifier, an input of the amplifier, and to a first diode-connected Metal Oxide Semiconductor Field Effect Transistor (MOSFET) connected in series to a second diode-connected MOSFET that is coupled to ground through a second switch (wherein the PDCTRL includes… coupled to ground through a second switch; claim 14, L9-13).
Regarding claim 13, US Pat 12,265,411 teaches at least one of the first diode-connected MOSFET and the second diode-connected MOSFET is a PMOS diode-connected MOSFET (claim 16).
Regarding claim 14, US Pat 12,265,411 teaches at least one of the first diode-connected MOSFET and the second diode-connected MOSFET is an NMOS diode-connected MOSFET (claim 17).
Regarding claim 15, US Pat 12,265,411 teaches the VREFGEN circuit is configured to transform the core power voltage into a current through a diode-connected MOSFET and a resistor in series and supply the difference between the IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM (claim 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-11, 17-18 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over anticipated by Melanson et al. (“Melanson”, US Pub 2022/0147082), in view of Luo et al. (“Luo”, US Pub 2016/0085250).
Regarding independent claim 1, Melanson teaches (Fig. 7; Para 76-85, 65, 67, 87, 103-106 & claim 7) a Low-Dropout voltage regulator (LDO) (i.e., LDO being 101-103: providing an output voltage Vout to a load 302; Para 57-60) comprising:
an amplifier (i.e., Amp 101 providing output voltage V1 to gate of N1, based on difference between reference voltage REF & feedback voltage Sfb; Para 57-60)
supplied with a voltage reference (VREFM) (i.e., REF: Fig. 3 shows controller CON 301 providing REF and Fig. 12 shows detail of CON 301), the amplifier (i.e., Amp 101)
configured to produce (i.e., V1) a source current to or a sinking current from a load (i.e. feedback Sfb used in Amp 101; or a load activity signal ‘ACT’, being any signal indicating a change in the activity of the load which results change in a change in the load current demand, thus activating 102 to source/sink current. Furthermore, 102 includes plurality of decoupling capacitors ‘nC’ that are selectively coupled to Va or ground to source or sink V1. V1 is then provided to transistor N1’s gate, and output of N1 is providing Vout to load 302; Para 76-77, 83-84 & claim 7);
a decoupling capacitor (i.e., output stage 102, includes plurality of decoupling capacitors ‘nC’ to source/sink V1),
connected to an output of the amplifier (i.e. V1 is output of Amp 101), and
configured to decouple a high-edge ground (HGND) from a power source (i.e. Va non-zero fixed or defined power supply voltage Va; Para 76-77, 83-84 & claim 7);
a power down control unit (PDCTRL) (i.e., controller CON 301 providing REF, and Fig. 12 shows detail of CON 301; Para 63 explaining two modes)
configured to maintain the HGND (i.e., Va non-zero fixed or defined power supply voltage Va)
in an active mode of the amplifier and in a power-down mode of the amplifier (Para 63, 76-77, 83-84 & claim 7); and
a VREFGEN circuit (anticipated circuit to provide REF) configured to supply the VREFM (REF) to the amplifier (Amp 101).
However, Melanson fails to teach the VREFGEN circuit configured to transform the core power voltage into a current through a diode-connected and a resistor in series and supply a difference between an IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM.
However, Luo teaches (Fig. 1-7; Para 26-51)
a VREFGEN circuit (Fig. 2-3; VREFGEN circuit being combined operation of ‘205, 210 (shown as 310), 230 (shown as 330)’) configured to supply the VREFM (Fig. 2-3; different powered (i.e., Vdd or Vreg) one of Vref 1 or Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) to the amplifier (Fig. 2; op-amp of LDO regulator 220),
the VREFGEN circuit (Fig. 2-3; VREFGEN circuit being combined operation of ‘205, 210 (shown as 310), 230 (shown as 330)’) configured to transform the core power voltage (i.e., Vdd powered Vref 1is selected to provide as Vref to op-amp of LDO regulator 220. Also, See, Fig. 7; apparatus or system 700 is shown to include various types of processors, CPU(s) and other elements, wherein modern processors/CPUs are known to include multi-cores operation to handle multiple jobs at the exact same time; and thus, Vdd is anticipated be a core power voltage) into a current (310 performs V (i.e., Vdd) to-I conversion, wherein currents being ‘Ib 101, Ib 103, Ib 105’ vs. 330 performs V (i.e., Vreg) to-I conversion, wherein currents being ‘Ib 102, Ib 104-105’)
through
a diode-connected MOSFET (M101, M103, M104-105: 310 includes diode-connected MOSFET(s) M103 (which is indirectly connected in series with a resistor R101, via M102) and M101 (which is directly connected in series with a resistor R101); and 330 includes diode-connected MOSFET(s) M105 (which is directly connected in series with a resistor R103) and M104) and
a resistor (R101-103: 310 includes diode-connected MOSFET(s) M103 (which is indirectly connected in series with a resistor R101, via M102) and M101 (which is directly connected in series with a resistor R101); and 330 includes diode-connected MOSFET(s) M105 (which is directly connected in series with a resistor R103) and M104) in series and
supply a difference (i.e., final provided Vref for LDO’s op-amp input) between
an IO power voltage (i.e., Vreg powered Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) and
the core power voltage (i.e., Vdd powered Vref 1is selected to provide as Vref to op-amp of LDO regulator 220. Also, See, Fig. 7; apparatus or system 700 is shown to include various types of processors, CPU(s) and other elements, wherein modern processors/CPUs are known to include multi-cores operation to handle multiple jobs at the exact same time; and thus, Vdd is anticipated be a core power voltage),
based on the current (310 performs V (i.e., Vdd) to-I conversion, wherein currents being ‘Ib 101, Ib 103, Ib 105’ vs. 330 performs V (i.e., Vreg) to-I conversion, wherein currents being ‘Ib 102, Ib 104-105’), to the amplifier (Fig. 2; op-amp of LDO regulator 220) as the VREFM (Fig. 2-3; different powered (i.e., Vdd or Vreg) one of Vref 1 or Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) to the amplifier (Fig. 2; op-amp of LDO regulator 220).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Melanson’s regulator to include the VREFGEN circuit configured to transform the core power voltage into a current through a diode-connected and a resistor in series and supply a difference between an IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM, disclosed by Lou, as doing so would have provided specific selection technique for different powered reference voltage, out of varied reference voltages, to be used by LDO’s amplifier, and by doing so improve overall power supply rejection ratio within the LDO regulator, meeting varied loads requirements, as taught by Lou (Para 1-4 and abstract).
Regarding claims 9, 18, Melanson teaches a Voltage Reference Generator (VREFGEN) circuit (i.e., REF: Fig. 3 shows controller CON 301 providing REF, and Fig. 12 shows detail of CON 301), configured to supply the VREFM to the amplifier (i.e., Amp 101), the VREFGEN configured to track or receive a fixed voltage reference (i.e. REF) and selectively supply the VREFM (i.e. REF) to the amplifier (i.e. Amp 101) as the VREFM (Para 76-77, 83-84 & claim 7).
Regarding claim 10, Melanson fails to teach the VREFM is directly forced by an input voltage or directly forced through the VREFGEN circuit that is configured to transfer a difference between the core power voltage and an IO power voltage.
However, Lou teaches the VREFM (Fig. 2-3; different powered (i.e., Vdd or Vreg) one of Vref 1 or Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) is directly forced by an input voltage (i.e., power) or directly forced through the VREFGEN circuit (i.e., Vreg that is passed that is used by 330) that is configured to transfer a difference (i.e., final provided Vref for LDO’s op-amp input) between the core power voltage (i.e., Vdd powered Vref 1is selected to provide as Vref to op-amp of LDO regulator 220. Also, See, Fig. 7; apparatus or system 700 is shown to include various types of processors, CPU(s) and other elements, wherein modern processors/CPUs are known to include multi-cores operation to handle multiple jobs at the exact same time; and thus, Vdd is anticipated be a core power voltage) and an IO power voltage (i.e., Vreg powered Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Melanson’s regulator to include the VREFGEN circuit configured to transform the core power voltage into a current through a diode-connected and a resistor in series and supply a difference between an IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM, disclosed by Lou, as doing so would have provided specific selection technique for different powered reference voltage, out of varied reference voltages, to be used by LDO’s amplifier, and by doing so improve overall power supply rejection ratio within the LDO regulator, meeting varied loads requirements, as taught by Lou (Para 1-4 and abstract).
Regarding independent claims ‘11, 17’ and dependent claim 15 (depending from claim 11), Melanson teaches (Fig. 7; Para 76-85, 65, 67, 87, 103-106 & claim 7) a Low-Dropout voltage regulator (LDO) (i.e., LDO being 101-103: providing an output voltage Vout to a load 302; Para 57-60) comprising:
an amplifier (i.e., Amp 101 providing output voltage V1 to gate of N1, based on difference between reference voltage REF & feedback voltage Sfb; Para 57-60) configured to produce (i.e., V1) a source current to or a sinking current from a load (i.e. feedback Sfb used in Amp 101; or a load activity signal ‘ACT’, being any signal indicating a change in the activity of the load which results change in a change in the load current demand, thus activating 102 to source/sink current. Furthermore, 102 includes plurality of decoupling capacitors ‘nC’ that are selectively coupled to Va or ground to source or sink V1. V1 is then provided to transistor N1’s gate, and output of N1 is providing Vout to load 302; Para 76-77, 83-84 & claim 7);
a Voltage Reference Generator (VREFGEN) circuit (anticipated circuit to provide REF) connected to a first input of the amplifier (Amp 101’s 1st input) and configured to track a fixed voltage reference (VREF) and supply a voltage reference output (VREFM) (i.e., REF: Fig. 3 shows controller CON 301 providing REF and Fig. 12 shows detail of CON 301) to the amplifier (Amp 101);
a decoupling capacitor (i.e., output stage 102, includes plurality of decoupling capacitors ‘nC’ to source/sink V1), connected to an output of the amplifier (i.e. V1 is output of Amp 101) and configured to decouple a high-edge ground (HGND) from a power source (i.e. Va non-zero fixed or defined power supply voltage Va; Para 76-77, 83-84 & claim 7); and
a Power Down Control Unit (PDCTRL) (i.e., controller CON 301 providing REF, and Fig. 12 shows detail of CON 301; Para 63 explaining two modes) configured to maintain the HGND (i.e., Va non-zero fixed or defined power supply voltage Va) in an active mode of the amplifier and in a power-down mode of the amplifier (Para 63, 76-77, 83-84 & claim 7).
However, Melanson fails to teach the VREFGEN circuit configured to receive the VREF and to determine a difference between a core power voltage and an Input/Output (IO) power voltage to supply the VREFM to the amplifier.
However, Luo teaches (Fig. 1-7; Para 26-51)
a VREFGEN circuit (Fig. 2-3; VREFGEN circuit being combined operation of ‘205, 210 (shown as 310), 230 (shown as 330)’) configured to supply the VREFM (Fig. 2-3; different powered (i.e., Vdd or Vreg) one of Vref 1 or Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) to the amplifier (Fig. 2; op-amp of LDO regulator 220),
the VREFGEN circuit (Fig. 2-3; VREFGEN circuit being combined operation of ‘205, 210 (shown as 310), 230 (shown as 330)’) configured to transform the core power voltage (i.e., Vdd powered Vref 1is selected to provide as Vref to op-amp of LDO regulator 220. Also, See, Fig. 7; apparatus or system 700 is shown to include various types of processors, CPU(s) and other elements, wherein modern processors/CPUs are known to include multi-cores operation to handle multiple jobs at the exact same time; and thus, Vdd is anticipated be a core power voltage) into a current (310 performs V (i.e., Vdd) to-I conversion, wherein currents being ‘Ib 101, Ib 103, Ib 105’ vs. 330 performs V (i.e., Vreg) to-I conversion, wherein currents being ‘Ib 102, Ib 104-105’)
through
a diode-connected MOSFET (M101, M103, M104-105: 310 includes diode-connected MOSFET(s) M103 (which is indirectly connected in series with a resistor R101, via M102) and M101 (which is directly connected in series with a resistor R101); and 330 includes diode-connected MOSFET(s) M105 (which is directly connected in series with a resistor R103) and M104) and
a resistor (R101-103: 310 includes diode-connected MOSFET(s) M103 (which is indirectly connected in series with a resistor R101, via M102) and M101 (which is directly connected in series with a resistor R101); and 330 includes diode-connected MOSFET(s) M105 (which is directly connected in series with a resistor R103) and M104) in series and
supply a difference (i.e., final provided Vref for LDO’s op-amp input) between
an IO power voltage (i.e., Vreg powered Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) and
the core power voltage (i.e., Vdd powered Vref 1is selected to provide as Vref to op-amp of LDO regulator 220. Also, See, Fig. 7; apparatus or system 700 is shown to include various types of processors, CPU(s) and other elements, wherein modern processors/CPUs are known to include multi-cores operation to handle multiple jobs at the exact same time; and thus, Vdd is anticipated be a core power voltage),
based on the current (310 performs V (i.e., Vdd) to-I conversion, wherein currents being ‘Ib 101, Ib 103, Ib 105’ vs. 330 performs V (i.e., Vreg) to-I conversion, wherein currents being ‘Ib 102, Ib 104-105’), to the amplifier (Fig. 2; op-amp of LDO regulator 220) as the VREFM (Fig. 2-3; different powered (i.e., Vdd or Vreg) one of Vref 1 or Vref 2 is selected to provide as Vref to op-amp of LDO regulator 220) to the amplifier (Fig. 2; op-amp of LDO regulator 220).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Melanson’s regulator to include the VREFGEN circuit configured to transform the core power voltage into a current through a diode-connected and a resistor in series and supply a difference between an IO power voltage and the core power voltage, based on the current, to the amplifier as the VREFM, disclosed by Lou, as doing so would have provided specific selection technique for different powered reference voltage, out of varied reference voltages, to be used by LDO’s amplifier, and by doing so improve overall power supply rejection ratio within the LDO regulator, meeting varied loads requirements, as taught by Lou (Para 1-4 and abstract).
27. Claims 2-4, 12-14 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over anticipated by Melanson (US Pub 2022/0147082), in view of Luo (US Pub 2016/0085250), Williams et al. (“Williams”, US Pub 2012/0187930) and Melanson et al. (“Melanson II”, US Pat 9419562).
28. Regarding claims 2, 12, Melanson and Lou fail to teach the PDCTRL includes a resistor connected at one end of the resistor to a core power voltage through a first switch and connected at another end of the resistor to the output of the amplifier, an input of the amplifier, and to a first diode-connected Metal Oxide Semiconductor Field Effect Transistor (MOSFET) connected in series to a second diode-connected MOSFET that is coupled to ground through a second switch.
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However, Williams teaches the PDCTRL (Fig. 1-4; i.e. ‘112, 103’ operable to control and stabilize Zload during different performance requirements by switching between three different modes, such as, normal mode, current limit mode and voltage foldback mode. Hence, regulator 100 is operable to increase or decrease (i.e. power down) output power; abstract)
includes a resistor (Fig. 3; i.e., 364) and a diode-connected MOSFET (Fig. 3; i.e., 362; para 34)
connected at one end of the resistor (Fig. 3; i.e., 364) to a core power voltage (Fig. 3; i.e., Vref_cf being based on ‘376 & 374, 370, 372, 368, 366’ combined operational output, wherein 376 receives load/core power feedback for biasing; Para 28) through a first switch (i.e., 110 or 360’s on/off operation) and
… the resistor (Fig. 3; i.e., 364) to the output of the amplifier (102’s output is received by 112, wherein 112’s detail in shown in Fig. 3), an (second) input of the amplifier (112’s output is used in 102), and at least one diode connected Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (Fig. 3; i.e., 362; para 34) that is coupled to ground.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to have modified Melanson and Lou’s PDCTRL controller to include a resistor being placed between the diode-connected MOSFET and a core power for biasing, as disclosed by Williams, as doing so would have provided a better controlled sensed current flow while ensuring less power consumption and thermal stress on the circuit components, and thus providing increased safety from thermal overload overall performance, as taught by Williams (Para 3-4, abstract).
However, Melanson & Williams fail to teach the specific use of a second switch to couple the ground from the core power voltage.
[NOTE. Applicant never claims any specific direct series connection or arrangements between all the components in PDCTRL, as described in Applicant’s Fig. 5. Examiner recommends to use specific node to claim actual series connection of all the claimed components in PDCTRL, as shown in Applicant’s Fig. 5]
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However, Melanson II teach (Fig. 4; col. 4 l7-Col. 5 L54) the specific use of a second switch (i.e., 412) to couple the ground (ground) from the core power voltage (1st switch 410 couples a core or power supply voltage & when on selects to provide that specific core or power voltage to the rest of the components in the series branch, wherein if the taught 2nd switch is on, then the series branch is grounded).
[NOTE. Applicant never claims any specific direct series connection or arrangements between all the components in PDCTRL, as described in Applicant’s Fig. 5. Examiner recommends to use specific node to claim actual series connection of all the claimed components in PDCTRL, as shown in Applicant’s Fig. 5]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to have modified Melanson, Luo & Williams collectively taught PDCTRL controller to include additional switches in a specific arrangement to selectively perform powering up (i.e., using the 1st switch) or grounding (using the 2nd switch) of the PDCTRL, as disclosed by Melanson II, as doing so would have provided an improved and precise periodical and cyclical operation of the PDCTRL, as taught by Melanson II (abstract).
29. Regarding claims 3-4, 13-14, Melanson teaches the PDCTRL (i.e., controller CON 301) operable to receive a core power (i.e., load 302 being battery powered devices; Para 48. Although, load being a core design is not explicitly mentioned, however, such specific loads are anticipated when using battery powered devices (like phone, laptop and or any portable devices, all of them includes processors and core designs)) for biasing (i.e. Fig. 12 shows 301 is able to receive Vout, Sfb, ACT for further adjustment/biasing purposes).
However, Melanson fails to teach the PDCTRL comprises a resistor and a diode-connected MOSFET wherein the diode-connected MOSFET is PMOS (as claimed in claims 3, 13) or NMOS (as claimed in claims 4, 14).
However, Williams teaches the PDCTRL (Fig. 1-4; i.e. ‘112, 103’ operable to control and stabilize Zload during different performance requirements by switching between three different modes, such as, normal mode, current limit mode and voltage foldback mode. Hence, regulator 100 is operable to increase or decrease (i.e. power down) output power; abstract) comprises a resistor (Fig. 3; i.e., 364) and a diode-connected MOSFET (Fig. 3; i.e., 362; para 34) wherein the diode-connected MOSFET is either PMOS (as claimed in claims 3, 13) or NMOS (as claimed in claims 4, 14) (Para 34), and wherein the resistor (Fig. 3; i.e., 364) is placed between the diode-connected MOSFET (Fig. 3; i.e., 362; para 34) and a core power for biasing (Fig. 3; i.e. Vref_cf being based on ‘376 & 374, 370, 372, 368, 366’ combined operational output, wherein 376 receives load/core power feedback for biasing; Para 28).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to have modified Melanson’s PDCTRL controller to include a resistor being placed between the diode-connected MOSFET and a core power for biasing, as disclosed by Williams, as doing so would have provided a better controlled sensed current flow while ensuring less power consumption and thermal stress on the circuit components, and thus providing increased safety from thermal overload overall performance, as taught by Williams (Para 3-4, abstract).
30. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over anticipated by Melanson (US Pub 2022/0147082), in view of Luo (US Pub 2016/0085250), Williams (US Pub 2012/0187930), Melanson II (US Pat 9419562) and Yang et al. (“Yang”, US Pub 2016/0173066).
31. Regarding claim 7, Melanson fails to teach the amplifier comprises includes a push-pull amplifier by using or having a push PMOS to the load and a pull NMOS from the load, wherein both MOS transistors share a drain connected to the load.
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Above Fig. 1, 3, 6 & 10 are from Yang et al. (“Yang”, US Pub 2016/0173066)
However, Yang teaches (Fig. 1, 3, 6, 10) the amplifier (Fig. 1, 3, 6; 110, 150 and 160; Para 62-63, 68, 93-85) comprises to drive a push PMOS (Fig. 6; i.e. push PMOS P2; Para 93-95) to the load and to drive a pull NMOS (Fig. 6; i.e., pull NMOS N2; Para 93-95) from the load (Fig. 1, 3; load 200), wherein both MOS transistors share a drain connected to the load (i.e., drains of both P2 & N2 are coupled to a node to adjust V1, which is coupled to gate of 130. Based on the gate voltage of 130, provides Vout to load 200).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Melanson’s various type amplifier to include and drive a push PMOS to the load and a pull NMOS from the load, using a gate bias from the amplifier, wherein both MOS transistors share a drain connected to the load, as disclosed by Yang, as doing so would have provided better control for providing sourcing and sinking current from the amplifier to and from load, respectively, while reducing positive and negative peaks of the power output at a faster speed, as taught by Yang (abstract).
32. Regarding claim 8, Melanson fails to teach a gate bias of the push PMOS and the pull NMOS is controlled by either a single amplifier or a dual amplifier.
However, Yang teaches a gate bias (i.e. Fug. 6; Vd) of the push PMOS (Fig. 6; i.e., push PMOS P2) and the pull NMOS (Fig. 6; i.e., pull NMOS N2) is controlled by either a single amplifier or a dual amplifier (Fig. 1; i.e., 110) (Para 62-63, 68, 93-85).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Melanson’s various type amplifier to include and drive a push PMOS to the load and a pull NMOS from the load, using a gate bias from the amplifier, wherein both MOS transistors share a drain connected to the load, as disclosed by Yang, as doing so would have provided better control for providing sourcing and sinking current from the amplifier to and from load, respectively, while reducing positive and negative peaks of the power output at a faster speed, as taught by Yang (abstract).
Allowable Subject Matter
Claims 5-6, 16, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5, 16, 19, Melanson teaches having a first and a second capacitors (i.e., 1st and 2nd capacitors being any two capacitors in the plurality of capacitors nC that are selectively coupled to Va or ground to source or sink V1, based on CON 301), except that one or more Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) (meaning, one of the two decoupling capacitor being PMOSCAP) is placed beneath (meaning, being in series connection) CMOM (meaning, another one of the two decoupling capacitor being CMOM) to get a highest capacitance density.
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Above Fig. 7-8 are from Aboudina et al. (“Aboudina”, US Pub 2016/0195883)
However, Aboudina et al. (“Aboudina”, US Pub 2016/0195883) teaches (Fig. 7-8, different implantation of resistors and capacitor in LDO; Para 53-54) capacitor(s) being based on P-type Metal Oxide Semiconductor Capacitor (PMOSCAP) technique (different types of p-channel or n-channel MOS type capacitor(s) can be used; Para 53-54).
However, Huang (US Pat 10768650) teaches having a decoupling capacitor (Fig. 4; Ccf2; col. 7 L7-12 and col. 2 L21-23) coupled to the output of amplifier (Fig. 4; i.e., 221) is based on a pure Metal-Oxide-Metal (MOM) capacitor (CMOM).
However, cited prior art(s) failed to teach “the first capacitor is a pure Metal-Oxide-Metal (MOM) capacitor (CMOM) connected at one end to the output of the amplifier and at another end to ground, and the second capacitor is a core P-type Metal Oxide Semiconductor Capacitor (PMOSCAP) connected at one end to the output of the amplifier and at another end to the core power voltage or to an Input/Output (IO) power voltage”, as claimed in claims 5, 16 and 19.
Claims 6, 20 are depending from claims 5 and 19, respectively.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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