Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 16 and 19
b. Pending: 1-20
Claims 21-23 are canceled through preliminary amendments.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 2/26/2025, 8/20/2025 and 9/23/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Fig. 4 and [0038] stated that plurality of ground selection transistors are connected in series. Independent claims 1, 16 and 19 lack this critical component.
Figs. 6A-6D and [0087]-[0088] describes that one ground selection transistor is connected in series in between first and third ground selection transistors and second and fourth ground selection transistors. The phrase “spaced apart” used in claim 1 is ambiguous and need to be clarified by introducing how and in which direction the elements in question are spaced apart.
Independent claims 1, 16 and 19 further simply recite ground selection transistors are turned off and turned on without any detail. Figs. 4A, 7 show specific way to set threshold voltage of ground selection transistors to one of the two voltage states according to GSL coding pattern. This is critical for the device to function and need to be incorporated into claim 1.
All the dependent claims 2-15 carry the same deficit and henceforth are rejected.
All the dependent claims 17-18 and 20 carry the same deficit and henceforth are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, 16-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibata et al. (US 20190122734).
Regarding independent claim 1, Shibata discloses a memory device (Fig. 1, [0050]-[0051]) comprising:
a substrate (10; Fig. 2, [0054]);
a first cell string on the substrate between a first bit line and a common source line (Fig. 20 shows SU1 between BL and SL), the first cell string including a first string selection transistor (STD1; Fig. 20 and [0272]) connected to a first string selection line (SGD1; Fig. 20 and [0272]); and
a second cell string on the substrate between the first bit line and the common source line (Fig. 20 shows SU4 between BL and SL), the second cell string including a second string selection transistor (STD4; Fig. 20 and [0275]) connected to a second string selection line (SGD4; Fig. 20 and [0275]),
wherein the first cell string (SU1; Fig. 20) includes:
a first ground selection transistor (STS0 of SU1; Fig. 20) connected to a first ground selection line (SGS0; Fig. 20); and
a third ground selection transistor (STS2 of SU1; Fig. 20) connected to a second ground selection line (SGS2; Fig. 20) and spaced apart from the first ground selection transistor (spaced apart by STS1 in between),
wherein the second cell string (SU4; Fig. 20) includes:
a second ground selection transistor (STS0 of SU4; Fig. 20) connected to the first ground selection line (SGS0; Fig. 20); and
a fourth ground selection transistor (STS2 of SU4; Fig. 20) connected to the second ground selection line (SGS2; Fig. 20) and spaced apart from the second ground selection transistor (spaced apart by STS1 in between), and
wherein, when the first cell string is a selected cell string (Fig. 22C and [0295] describes when the string unit SU1 is selected), the second ground selection transistor and the fourth ground selection transistor in the second cell string are configured to be turned off (Fig. 22C shows SGS0 and SGS2 of SU1 at “L” state. Fig. 20 shows STS0 and STS4 of SU4 are Enhancement type transistors and [0289] describes “L” level will turn off STS0 and STS4 of SU4), and at least one ground selection transistor between the second ground selection transistor and the fourth ground selection transistor in the second cell string is configured to be turned on (Fig. 20 shows STS1 of SU4 is Depletion type transistor. Since SGS1 of SU1 is at “H” state, so STS1 of SU4 will be turned on).
Regarding claim 2, Shibata discloses all the elements of claim 1 as above and further the first cell string includes: a fifth ground selection transistor connected to a third ground selection line; and a seventh ground selection transistor connected to a fourth ground selection line, wherein the second cell string includes: a sixth ground selection transistor connected to the third ground selection line, and an eighth ground selection transistor connected to the fourth ground selection line, wherein the third ground selection line is between the first ground selection line and the second ground selection line, and wherein the second ground selection line is between the third ground selection line and the fourth ground selection line (Fig. 20 shows additional ground selection transistors, each connected to additional ground selection lines).
Regarding claim 3, Shibata discloses all the elements of claim 2 as above and further the second cell string is the selected cell string (SU4; Fig. 20), the fifth ground selection transistor and the seventh ground selection transistor in the first cell string are configured to be turned off, and at least one ground selection transistor between the fifth ground selection transistor and the seventh ground selection transistor in the first cell string is configured to be turned on (Figs. 20, 22C shows when SU4 is selected, their corresponding ground selection transistors as on and/or off).
Regarding claim 4, Shibata discloses all the elements of claim 3 as above and further the memory device includes: a third cell string on the substrate between the first bit line and the common source line (Fig. 20 shows SU3 between BL and SL), the third cell string including a third string selection transistor connected to a third string selection line (STD3; Fig. 20 and [0171]), and wherein the third cell string includes: a ninth ground selection transistor connected to the first ground selection line; a tenth ground selection transistor connected to the second ground selection line; an eleventh ground selection transistor connected to the third ground selection line; and a twelfth ground selection transistor connected to the fourth ground selection line (Fig. 20 shows multiple ground selection transistors connected to corresponding multiple ground selection lines).
Claims 5-8 are basically minor variations of claims 1-3 without any innovative steps associated.
Regarding claim 9, Shibata discloses all the elements of claim 2 as above and further a first threshold voltage state of the first ground selection transistor is lower than a second threshold voltage state of the second ground selection transistor, wherein a third threshold voltage state of the third ground selection transistor is lower than a fourth threshold voltage state of the fourth ground selection transistor, wherein a fifth threshold voltage state of the fifth ground selection transistor is higher than a sixth threshold voltage state of the sixth ground selection transistor, and wherein a seventh threshold voltage state of the seventh ground selection transistor is higher than an eighth threshold voltage state of the eighth ground selection transistor (Figs. 20, 22B shows types (depletion/enhancement) and threshold voltage relationship of various ground selection transistors).
Regarding claim 10, Shibata discloses all the elements of claim 9 as above and further when the first cell string is the selected cell string (Fig. 22C shows when SU1 is selected), the memory device is configured to apply a first voltage to the first ground selection line, apply a second voltage to the second ground selection line, apply a third voltage to the third ground selection line, and apply a fourth voltage to the fourth ground selection line, wherein the first voltage is higher than the first threshold voltage state and is lower than the second threshold voltage state, wherein the second voltage is higher than the third threshold voltage state and is lower than the fourth threshold voltage state, wherein the third voltage is higher than the fifth threshold voltage state, and wherein the fourth voltage is higher than the seventh threshold voltage state (Fig. 22C shows LHLH pattern for SGS0 through SGS3 lines).
Regarding claim 11, Shibata discloses all the elements of claim 10 as above and further the first voltage is same as the second voltage, and wherein the third voltage is same as the fourth voltage (Fig. 22C shows LHLH pattern for SGS0 through SGS3 lines).
Regarding claim 12, Shibata discloses all the elements of claim 9 as above and further the first threshold voltage state, the third threshold voltage state, the sixth threshold voltage state, and the eighth threshold voltage state are the same, and wherein the second threshold voltage state, the fourth threshold voltage state, the fifth threshold voltage state, and the seventh threshold voltage state are the same (Fig. 20 shows STS1, STS3 of SU1 and STS2, STS4 of SU4 are enhancement type transistors. Also, STS0, STS2 of SU1 and STS1, STS3 of SU4 are depletion type transistors).
Independent claim 16 is drafted slightly different way than independent claim 1 and henceforth rejected the same way.
Claim 17 depends on claim 16 and recites same limitations of claim 3 drafted differently and henceforth rejected the same way.
Independent claim 19 is a combination of independent claim 1 and claim 3 but drafted differently and henceforth rejected the same way as claim 1 and 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US 20190122734) in view of Kim et al. (US 20240203509).
Regarding claim 14, Shibata discloses all the elements of claim 1 as above and through Kim further a dummy ground selection line is between the first ground selection line and the second ground selection line, wherein the first cell string includes a first dummy ground selection transistor connected to the dummy ground selection line, and wherein the second cell string includes a second dummy ground selection transistor connected to the dummy ground selection line (Figs. 6-7 and [0080], [0086]-[0088] shows usage of dummy ground selection lines in between regular ground selection lines).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kim to Shibata in order to provide with memory device for increasing integration density and the reliability of data and an operating method as taught by Kim ([0006]).
Regarding claim 15, Shibata and Kim together disclose all the elements of claim 14 as above and further when the first cell string or the second cell string is the selected cell string, the first dummy ground selection transistor and the second dummy ground selection transistor are configured to be turned on (Figs. 20, 22C of Shibata and Figs. 6-7 of Kim along with corresponding sections of the Specifications).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kim to modified Shibata in order to provide with memory device for increasing integration density and the reliability of data and an operating method as taught by Kim ([0006]).
Claim 18 depends on claim 16 and recites the same claim limitations of claim 14 but drafted differently. Henceforth claim 18 is rejected the same way as claim 14.
Claim 20 depends on claim 19 and recites the same claim limitations of claim 14 but drafted differently. Henceforth claim 20 is rejected the same way as claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nam et al. (US 20120224426)
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 8/6/2026
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