Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on February 26, 2025
2. Claims 1-20 are pending and has been examined.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 02/26/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. Drawings are submitted on 02/06/2025 are acceptable.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16 and 19-20 are rejected under 35 U.S.C. 103 as being obvious over Soenen “8598854” in a view of Jain “9323263”.
In re to claim 13 , Soenen discloses an input/output device (Fig. 8 :DC-DC converter 800 includes Vin and Vout) , comprising: a first voltage level shifter (shifter PLVSFT) and a second voltage level shifter (shifter NLVSFT) configured to respectively receive first signals in a first voltage range (Vp and Vn respectively) and output second signals in a second voltage range (output from shifter PLVSFT and shifter NLVSFT); a first logic circuit (PDRV) and a second logic circuit (NDRV) configured to receive different supply voltages (PRDV receives voltage Vsup & LS and NPRDV receives HS & ground) and to respectively output switching signals (signals to drive switches N8 and N9) according to the second signals (output signal from shifter PLVSFT and NLVSFT) ; and provided to one or more of the first logic circuit (PRDV) and the second logic circuit (NDRV) and the first and second voltage level shifters (PLVSFT and NLVSFT).
Furthermore, Soenen reference disclosure is generally related to LDO (low-dropout) regulators implements in DC-DC regulator (col. 6, lines 28-62) and Various embodiments use a charge pump in conjunction with a source follower to form a regulator, see abstract).
However, Jain fails to discloses a low dropout regulator comprising a plurality of current paths and configured to regulate a power supply voltage provided to one or more of the first logic circuit and the second logic circuit and the first and second voltage level shifters, wherein the low dropout regulator comprises a plurality of hysteresis comparators configured to separately turn on or off switches in the plurality of current paths.
Whereas, Jian discloses a low dropout regulator (Figs. 1-11: low dropout (LDO) regulator) comprising a plurality of current paths (current path thru first ,second and third stage 201-203) and configured to regulate a power supply voltage (Vin), wherein the low dropout regulator comprises a plurality of hysteresis comparators (hysteresis unit 103 includes first and second comparators 206-207 ) configured to separately turn on or off switches in the plurality of current paths (second stage 202 provides overshoot protection to the node Vout and is normally turned on i.e., the p-type transistor MP1.sub.2 is normally turned on and is turned off by the hysteresis unit 103 if overshoot is detected on the node Vout and third stage 203 provides undershoot protection to the node Vout and is normally turned off i.e., the p-type transistor MP1.sub.3 is normally turned off and is turned on by the hysteresis unit 103 if undershoot is detected on the node Vout, see , col. 4, lines 14-42 and col. 14 ,lines 44-46).
It would have been obvious to one of ordinary skilled person in the art before the filing dated of the invention to modify the DC-DC converter of Soenen to include LDO as taught by Jain because implementing a Low Dropout (LDO) regulator after a DC-DC switching converter creates a hybrid power system.This setup uses the DC-DC converter for high-efficiency bulk voltage reduction, while the LDO cleans up the remaining high-frequency switching noise and ripple to power sensitive analog, RF, or audio components , thus improve the reliability of the system.
In re to claim 14, Soenen as modified discloses (Fig. 8) , the input/output device (Fig. 8 of Jian discloses Vin and Vout) .
Furthermore, Soenen discloses wherein the low dropout regulator (Figs. 1-11 of Soenen reference discloses LDO) comprises: a voltage divider circuit (resistor Rload : it is understood/ implicit in the art that voltage divider is configured to LDO to stabilize the system performance, and reduces signal distortion) configured to generate a feedback voltage (Figs. 2 and 6: vout) according to the power supply voltage (Vin); an operational amplifier (amplifier 101) configured to output a driving signal (output signal from 101) according to the feedback voltage (Vout) and a reference voltage (Vref) ; and a pass gate circuit ( output stage 102) comprising the plurality of current paths (current path thru first ,second and third stage 201-203), wherein each of the plurality of current paths comprises a transistor and a switch connected in series (Fig. 6: MP2.sub.1, MP2.sub.2, and MP2.sub.3 and MN1.sub.1, MN1.sub.2, and MN1.sub.3 connected in series correspondingly ), the transistors in the plurality of current paths including gate terminals connected to an output terminal of the operational amplifier to receive the driving signal (gate of MP2.sub.1, MP2.sub.2, and MP2.sub.3 are coupled to output of opamp 101), and the switches in the plurality of current paths configured to be separately turned on or off ( Vout_high and Vout_low_b, see Figs.2 -3 and 6) to separately turn on or off the plurality of switches in the plurality of current paths in response to the driving signal (second stage 202 provides overshoot protection to the node Vout and is normally turned on i.e., the p-type transistor MP1.sub.2 is normally turned on and is turned off by the hysteresis unit 103 if overshoot is detected on the node Vout and third stage 203 provides undershoot protection to the node Vout and is normally turned off i.e., the p-type transistor MP1.sub.3 is normally turned off and is turned on by the hysteresis unit 103 if undershoot is detected on the node Vout, see , col. 4, lines 14-42 and col. 14 ,lines 44-46.)
In re to claim 15, Soenen as modified (fig. 8) discloses the input/output device .
Furthermore, Jian discloses the pass gate circuit is configured to operate in a plurality of modes (see , col. 4, lines 14-42 and col.14 ,lines 44-46), the switches in the plurality of current paths being separately turned on or off according to a selected one of the plurality of modes (see, col. 4, lines 14-42 and col. 14 ,lines 44-46. Examiner noted that ON and OFF of the plurality switches is equivalent to plurality of modes
In re to claim 16, Soenen as modified (fig. 8) discloses the input/output device Furthermore, Jian discloses , the selected one of the plurality of modes is determined according to a toggle rate calculated based on a clock signal (first and second comparators 206 and 207 are clocked comparators, see col. 14, lines 44-47).
In re to claim 19, Soenen as modified (fig. 8) discloses the input/output device wherein the first logic circuit (PDRV) and the second logic circuit (NDRV) form a decoding circuit to generate the switching signals (high “1” and low “0” signals ) for driving a post driver circuit (switch N8 and N9) coupled to the first logic circuit and the second logic circuit (PDRV and NDRV).
In re to claim 20, Soenen as modified (fig. 8) discloses the input/output device, wherein the first logic circuit and the second logic circuit comprise buffer or inverter circuits to generate the switching signals according to the second voltage signals from the first and second voltage level shifters (PDRV and NDRV. Examiner noted prior art uses first and second shifter PDRV and NDRV based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome. Therefore, any skilled person designing the circuit of “Jian Fig. 8” would have to exercise a routine experiment, thereby arriving to the subject matter of claim 20).
Allowable Subject Matter
6. In re to claim 1, Jain discloses a circuit (Figs. 1-11: low dropout (LDO) regulator with hysteresis unit) , comprising: an operational amplifier (Figs. 2 and 6: amplifier 101) configured to output a driving signal (output signals from amplifier 101) according to a feedback voltage associated with an output voltage (Vout) and a reference voltage (Vref);
a pass gate circuit ( output stage 102) comprising a plurality of switches ( first ,second and third stage 201-203 includes MP1.sub.1 -MP1.sub. 3) in a plurality of current paths (current path thru first ,second and third stage/legs 201-203) ; and a plurality of hysteresis comparators (hysteresis unit 103 includes first and second comparators 206-207 ) connected to the operational amplifier (101 ) and configured to generate control signals ( Vout_high and Vout_low_b, see Figs.2 -3 and 6) to separately turn on or off the plurality of switches in the plurality of current paths in response to the driving signal (second stage 202 provides overshoot protection to the node Vout and is normally turned on i.e., the p-type transistor MP1.sub.2 is normally turned on and is turned off by the hysteresis unit 103 if overshoot is detected on the node Vout and third stage 203 provides undershoot protection to the node Vout and is normally turned off i.e., the p-type transistor MP1.sub.3 is normally turned off and is turned on by the hysteresis unit 103 if undershoot is detected on the node Vout, see , col. 4, lines 14-42 and col. 14 ,lines 44-46) .
The only difference between Jain and the invention claims are the comparators configured to generated control signals in response to the driving signals.
In regards to claims 1 and 7, the claims recites the plurality of hysteresis configured to generate control signals in response to the driving signals which is Vpass outputted from the opamp (210) .
In Jian’s reference the plurality of hysteresis comparators configured to generate control signals in response output voltage (vout) and reference voltage (Vref).
Therefore, Jian fails to discloses the plurality of hysteresis comparators in response to the driving signals (Vpass).
7. Claims 1-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowed because the prior art in the records fails to disclose or suggest a circuit including the limitation of “…operational amplifier and configured to generate control signals to separately turn on or off the plurality of switches in the plurality of current paths in response to the driving signal…”
Claim 7 is allowed because the prior art in the records fails to disclose or suggest a circuit including the limitation of “..a plurality of hysteresis comparators, control signals in response to the driving signal to separately turn on or off a plurality of switches in a plurality of current paths of a pass gate circuit…”
Claims 2-6 are dependent on claim 1, thus are also allowed because of their dependency.
8. Claims 8-12 are dependent on claim 7, thus are also allowed because of their dependency.
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 is objected because the prior art in the records fails to disclose or suggest a circuit including the limitation of “a hysteresis comparator connected to the operational amplifier and configured to compare the driving signal with a second reference voltage to separately turn on or off the switches in the plurality of current paths.”
Claim 18 are dependent on claim 17, thus is also objected because of its dependency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
Prosecution Insights