DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0193832A1) in view of Lee et al. (US 2025/0014984A1).
With respect to claim 1, Chen describes a method comprising: providing a base structure including gate electrodes 94, 98 on a substrate 50 and gate dielectric layer 100 covering the gate electrodes 94, 98 (fig. 15B, 15C; para 34, 37, 38)
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478
790
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; forming a via opening extending from an upper surface of the base structure to expose the gate dielectric layer 100 (fig. 17B, 17C; para 42)
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554
808
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; performing an etching by avoiding using a plasma such as a wet etching process or non-plasma etching process on the gate dielectric layer 100 through the via opening to expose a portion of the gate electrodes 94, 98 (fig. 18B, 18C; para 44)
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526
814
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; forming an electrical connector 174 including barrier 170 and metallic material 172 or claimed conductive cap on the portion of the gate electrode, which would prevent the gate electrode from being exposed through the via opening (fig. 26A; para 53-55)
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522
712
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.
Unlike claimed invention, Chen doesn’t teach the non-plasma etching process and formation of the electrical connector being performed without breaking a vacuum. Lee teaches a processing apparatus having wet etch tool, dry etch tool, deposition tool where wafer can be transferred between the processing tools without breaking the vacuum (para 22, 26-28; fig. 1, 2). It would have been obvious for one skilled in the art before the effective filing date of the invention to perform the non-plasma etching and forming of the electrical connector without breaking the vacuum because Lee teaches that it prevents and reduce the likelihood of contamination of semiconductor devices (para 28).
With respect to claim 8, Chen teaches the metal materials include W (para 54).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Lee as applied to claim 1 above, and further in view of Yamate (US 2021/0347726A1).
With respect to claim 7, Chen doesn’t teach forming the barrier170 and metal material 172 with thermal CVD. However, thermal CVD is a known-method for depositing barrier and conductive film as shown here by Yamate (para 97). Therefore, it would have been obvious for one skilled in the art before the effective filing date of the invention to use known method such as thermal CVD for deposition of the barrier and conductive layer because using known method without changes in their respective functions would form the barrier and the conductive metal material with expected results.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Lee as applied to claim 1 above, and further in view of Demichi et al. (US 2016/0020115A1).
With respect to claim 6, Chen doesn’t teach the non-plasma etching of the dielectric layer 100 including a BSG layer (para 38) is done at a pressure from 0.1 torr to 10 torr. However, an etching pressure would depend on the type of non-plasma process is being done. Demichi teaches an example for etching a BSG wherein an interval pressure of the chamber is from 0.5 to 1 torr (para 67). Therefore, it would have been obvious for one skilled in the art before the effective filing date of the invention to provide an appropriate etching pressure such as from 0.1 torr to 10 torr, depending on a type of non-plasma process being applied, such as one taught by Demichi, so that the dielectric layer BSG can be removed with expected results.
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2 and its dependent claims 4-5 are allowable because Chen doesn’t teaches the non-plasma etching the dielectric layer 100 includes at least one etch cycle, in which a first halogen-containing gas and a second halogen-containing gas are sequentially applied on the gate dielectric layer in such order, such that a surface region of the gate dielectric layer exposed to the via opening is removed after each cycle of the at least one etch cycle, and a halogen element in the first halogen-containing gas is different from a halogen element in the second halogen-containing gas.
Claims 9-12 are allowed allowable because Chen doesn’t teaches the non-plasma etching the dielectric layer 100 “including subjecting the surface region of the gate dielectric layer to react with a first halogen-containing gas so as to form a first film, the first halogen-containing gas containing a first halogen, performing an atomic layer clean treatment which includes subjecting the first film to react with a second halogen-containing gas, so as to remove the first film and to form a second film different from the first film, the second halogen-containing gas containing a second halogen different from the first halogen, and subjecting the second film to react with the first halogen-containing gas, so as to remove the second film and to form the first film, and repeating the atomic layer clean treatment until the portion of the gate electrode is exposed through the via opening” in combination with other limitations of claim 9.
Claims 13-20 are allowed because Chen, even though teaches a structure including channel region between source/drain regions 82 and 84 (para 32) and dielectric layer 100 on gate electrodes 94, 98; however he doesn’t teach forming a based structure including “channel portions which are vertically stacked and spaced apart from each other, a protection portion which is disposed on and spaced apart from an uppermost one of the channel portions, a gate dielectric layer which includes a first dielectric portion disposed beneath the protection portion and a second dielectric portion disposed around the channel portions, and a gate electrode disposed on the gate dielectric layer to fill spaces each of which is located between two corresponding adjacent ones of the channel portions and the protection portion” and the steps of “forming a via opening which penetrates the protection portion to terminate at the first dielectric portion; performing a non-plasma etching process on the first dielectric portion through the via opening until the via opening penetrates the first dielectric portion to expose a portion of the gate electrode” in combination with other limitations of claim 13.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY VU NGUYEN DEO whose telephone number is (571)272-1462. The examiner can normally be reached 9-5 M-F.
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/DUY VU N DEO/Primary Examiner, Art Unit 1713
9/28/2026
