Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Double Patenting
3. A rejection based on double patenting of the "same invention" type finds its support in the language of 35 U.S.C. 101 which states that "whoever invents or discovers any new and useful process... may obtain a patent therefor..." (Emphasis added). Thus, the term "same invention," in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 1 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12243491 B2. This is a statutory double patenting rejection.
Present application (19065461) US Patent 12243491 B2
Claim 1
Claim 1
A display panel comprising:
A display panel comprising:
a base layer including a display region and a non-display region disposed adjacent to the display region;
a base layer including a display region and a non-display region disposed adjacent to the display region;
a plurality of insulation layers disposed on the non-display region;
a plurality of insulation layers disposed on the non-display region;
a pixel circuit disposed on the display region;
a pixel circuit disposed on the display region;
a light emitting element disposed on the display region and electrically connected to the pixel circuit;
a light emitting element disposed on the display region and electrically connected to the pixel circuit;
a shielding electrode disposed on the non-display region; and
a shielding electrode disposed on the non-display region; and
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
wherein the first transistor includes:
wherein the first transistor includes:
a first semiconductor pattern layer including:
a first semiconductor pattern layer including:
a first input region,
a first input region,
a first output region, and
a first output region, and
a first channel region disposed between the first input region and the first output region, the first channel region overlapping the shielding electrode;
a first channel region disposed between the first input region and the first output region, the first channel region overlapping the shielding electrode;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping each of the first channel region and the shielding electrode;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping each of the first channel region and the shielding electrode;
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second input region electrically connected to the first input region through a first contact hole,
a second input region electrically connected to the first input region through a first contact hole,
a second output region electrically connected to the first output region through a second contact hole, and
a second output region electrically connected to the first output region through a second contact hole, and
a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and
a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, and
wherein, in a view perpendicular to an upper surface of the base layer, the shielding electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
wherein, in a view perpendicular to an upper surface of the base layer, the shielding electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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