Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 04/14/2026 has been entered. Claim 1 has been amended. Claims 2-20 have been added. Claims 1-20 remain pending in the application.
Obviousness-Type Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761(CCPA1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).
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4. Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12243491 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Present application (19065461) US Patent 12243491 B2
Claim 1
Claim 1
An electronic device comprising: a display device, wherein the display device comprises:
A display panel comprising:
a base layer including a display region and a non-display region disposed adjacent to the display region;
a base layer including a display region and a non-display region disposed adjacent to the display region;
a plurality of insulation layers disposed on the non-display region;
a plurality of insulation layers disposed on the non-display region;
a pixel circuit disposed on the display region;
a pixel circuit disposed on the display region;
a light emitting element disposed on the display region and electrically connected to the pixel circuit;
a light emitting element disposed on the display region and electrically connected to the pixel circuit;
a shielding electrode disposed on the non-display region; and
a shielding electrode disposed on the non-display region; and
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
wherein the first transistor includes:
wherein the first transistor includes:
a first semiconductor pattern layer including:
a first semiconductor pattern layer including:
a first input region,
a first input region,
a first output region, and
a first output region, and
a first channel region disposed between the first input region and the first output region, the first channel region overlapping the shielding electrode;
a first channel region disposed between the first input region and the first output region, the first channel region overlapping the shielding electrode;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping each of the first channel region and the shielding electrode;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping each of the first channel region and the shielding electrode;
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second input region electrically connected to the first input region through a first contact hole,
a second input region electrically connected to the first input region through a first contact hole,
a second output region electrically connected to the first output region through a second contact hole, and
a second output region electrically connected to the first output region through a second contact hole, and
a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and
a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, and
wherein, in a view perpendicular to an upper surface of the base layer, the shielding electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
wherein, in a view perpendicular to an upper surface of the base layer, the shielding electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
As shown in the comparison above, the instant application claim 1 is broader in every aspect than the patent claim 1 of US 12243491 B2 and is therefore an obvious variant thereof. Claims 2 recite the same limitation as claim 2 of US 12243491 B2, and therefore are rejected.
5. Claims 3-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-14 of U.S. Patent No. 12243491 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Present application (19065461) US Patent 12243491 B2
Claim 10
Claim 3
An electronic device display panel comprising: a display device, wherein the display device comprises:
A display panel, comprising:
a base layer including a display region and a non-display region adjacent to the display region;
a base layer including a display region and a non-display region adjacent to the display region;
a plurality of insulation layers disposed on the non-display region;
a plurality of insulation layers disposed on the non-display region;
a pixel circuit disposed on the display region;
a pixel circuit disposed on the display region;
a light emitting element disposed on the display region and electrically connected to the pixel circuit; and
a light emitting element disposed on the display region and electrically connected to the pixel circuit; and
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
herein the first transistor includes:
a first semiconductor pattern layer including:
a first input region,
a first output region, and
a first channel region disposed between the first input region and the first output region;
wherein the first transistor includes:
a first semiconductor pattern layer including:
a first input region,
a first output region, and
a first channel region disposed between the first input region and the first output region;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping the first channel region;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping the first channel region;
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second input region electrically connected to the first input region,
a second output region electrically connected to the first output region, and
a second channel region disposed between the second input region and the second output region, the second channel region overlapping the first channel region; and
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second input region electrically connected to the first input region,
a second output region electrically connected to the first output region, and
a second channel region disposed between the second input region and the second output region, the second channel region overlapping the first channel region; and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode,
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode,
wherein the pixel circuit comprises:
wherein the pixel circuit comprises:
a first-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the first semiconductor pattern layer is disposed and including a same oxide semiconductor as the first semiconductor pattern layer; and
a first-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the first semiconductor pattern layer is disposed and including a same oxide semiconductor as the first semiconductor pattern layer; and
a second-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the second semiconductor pattern layer is disposed and including a same oxide semiconductor as the second semiconductor pattern layer, and
a second-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the second semiconductor pattern layer is disposed and including a same oxide semiconductor as the second semiconductor pattern layer, and
wherein at least one of the first-type transistor and the second-type transistor is configured to receive the scan signal.
wherein at least one of the first-type transistor and the second-type transistor is configured to receive the scan signal.
As shown in the comparison above, the instant application claim 10 is broader in every aspect than the patent claim 3 of US 12243491 B2 and is therefore an obvious variant thereof. Claims 3-9 and 11-14 recite the same limitation as claims 4-14 of US 12243491 B2, and therefore are rejected.
6. Claims 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-20 of U.S. Patent No. 12243491 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Present application (19065461) US Patent 12243491 B2
Claim 15
Claim 15
An electronic device comprising: a display device, wherein the display device comprises:
A display panel comprising:
a base layer including a display region and a non-display region disposed adjacent to the display region;
a base layer including a display region and a non-display region disposed adjacent to the display region;
a plurality of insulation layers disposed on the non-display region;
a plurality of insulation layers disposed on the non-display region;
a pixel circuit disposed on the display region;
a pixel circuit disposed on the display region;
a light emitting element disposed on the display region and electrically connected to the pixel circuit; and
a light emitting element disposed on the display region and electrically connected to the pixel circuit; and
a scan driving circuit disposed on the non-display region, the scan driving circuit including:
a scan driving circuit disposed on the non-display region, the scan driving circuit including:
a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor, and
a second transistor configured to output the scan signal of a second logic level during a turn-on period of the second transistor, the second logic level being different from the first logic level,
a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor, and
a second transistor configured to output the scan signal of a second logic level during a turn-on period of the second transistor, the second logic level being different from the first logic level,
wherein the first transistor includes:
a plurality of first semiconductor pattern layers extending in a first direction and arranged in a second direction intersecting the first direction, each of the plurality of first semiconductor pattern layers including:
a first input region,
a first output region,
a first channel region disposed between the first input region and the first output region,
a 1-1 input region, and
a 1-1 channel region disposed between the 1-1 input region and the first output region;
wherein the first transistor includes:
a plurality of first semiconductor pattern layers extending in a first direction and arranged in a second direction intersecting the first direction, each of the plurality of first semiconductor pattern layers including:
a first input region,
a first output region,
a first channel region disposed between the first input region and the first output region,
a 1-1 input region, and
a 1-1 channel region disposed between the 1-1 input region and the first output region;
a first gate electrode disposed on the plurality of first semiconductor pattern layers, the first gate electrode including:
a first portion overlapping the first channel region of each of the plurality of first semiconductor pattern layers, and
a second portion overlapping the 1-1 channel region of each of the plurality of first semiconductor pattern layers;
a first gate electrode disposed on the plurality of first semiconductor pattern layers, the first gate electrode including:
a first portion overlapping the first channel region of each of the plurality of first semiconductor pattern layers, and
a second portion overlapping the 1-1 channel region of each of the plurality of first semiconductor pattern layers;
a plurality of second semiconductor pattern layers disposed to correspond to the plurality of first semiconductor pattern layers, each of plurality of second semiconductor pattern layers including:
a second input region electrically connected to the first input region,
a second output region electrically connected to the first output region,
a second channel region disposed between the second input region and the second output region and overlapping the first channel region,
a 2-1 input region electrically connected to the 1-1 input region, and
a 2-1 channel region disposed between the 2-1 input region and the second output region and overlapping the 1-1 channel region; and
a plurality of second semiconductor pattern layers disposed to correspond to the plurality of first semiconductor pattern layers, each of plurality of second semiconductor pattern layers including:
a second input region electrically connected to the first input region,
a second output region electrically connected to the first output region,
a second channel region disposed between the second input region and the second output region and overlapping the first channel region,
a 2-1 input region electrically connected to the 1-1 input region, and
a 2-1 channel region disposed between the 2-1 input region and the second output region and overlapping the 1-1 channel region; and
a second gate electrode disposed on the plurality of second semiconductor pattern layers, the second gate electrode including:
a third portion overlapping the second channel region of each of the plurality of second semiconductor pattern layers, and
a fourth portion overlapping the 2-1 channel region of each of the plurality of second semiconductor pattern layers.
a second gate electrode disposed on the plurality of second semiconductor pattern layers, the second gate electrode including:
a third portion overlapping the second channel region of each of the plurality of second semiconductor pattern layers, and
a fourth portion overlapping the 2-1 channel region of each of the plurality of second semiconductor pattern layers.
As shown in the comparison above, the instant application claim 15 is broader in every aspect than the patent claim 15 of US 12243491 B2 and is therefore an obvious variant thereof. Claims 16-20 and 11-14 recite the same limitation as claims 16-20 of US 12243491 B2, and therefore are rejected.
Allowable Subject Matter
7. Claims 1-20 would be allowable if double patenting rejections are overcome. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a gate driver including thin film transistors for driving a display panel. The closet prior arts, Ko (US 20230061581A1), Lee (US 20230361189 A1), Matsukizono (US 20190273168 A1), Kim (US 20210057458 A1), and Liu (US 20220415933 A1), individually or in combination, discloses a display panel comprising: a base layer including a display region and a non-display region disposed adjacent to the display region; a plurality of insulation layers disposed on the non-display region of the base layer; a pixel circuit disposed on the display region of the base layer; a light emitting element disposed on the display region of the base layer and electrically connected to the pixel circuit; and a scan driving circuit disposed on the non-display region of the base layer, the scan driving circuit including: a first transistor that outputs a high-voltage of a scan signal during a turn-on period of the first transistor, and a second transistor that outputs a low-voltage of the scan signal during a turn-on period of the second transistor, wherein the first transistor includes: a plurality of first semiconductor pattern layers extending in a first direction and arranged in a second direction intersecting the first direction, each of the plurality of first semiconductor pattern layers including: a first input region, a first output region, a first channel region disposed between the first input region and the first output region; a first gate electrode disposed on the plurality of first semiconductor pattern layers, the first gate electrode including: a first portion overlapping the first channel region of each of the plurality of first semiconductor pattern layers; a plurality of second semiconductor pattern layers disposed to correspond to the plurality of first semiconductor pattern layers, each of plurality of second semiconductor pattern layers including: a second input region electrically connected to the first input region, a second output region electrically connected to the first output region, a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and a second gate electrode disposed on the plurality of second semiconductor pattern layers, the second gate electrode including: a third portion overlapping the second channel region of each of the plurality of second semiconductor pattern layers. However, the closet prior arts fail to teach wherein the pixel circuit comprises: a first-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the first semiconductor pattern layer is disposed and including a same oxide semiconductor; and a second-type transistor including a semiconductor pattern layer disposed on a same layer as a layer on which the second semiconductor pattern layer is disposed and including a same oxide semiconductor, wherein at least one of the first-type transistor and the second-type transistor is configured to receive the scan signal. In addition, the closet prior arts fail to teach each of the plurality of first semiconductor pattern layers further including a 1-1 input region, and a 1-1 channel region disposed between the 1-1 input region and the first output region, the first gate electrode further including a second portion overlapping the 1-1 channel region of each of the plurality of first semiconductor pattern layers, each of plurality of second semiconductor pattern layers further including a 2-1 input region electrically connected to the 1-1 input region, and a 2-1 channel region disposed between the 2-1 input region and the second output region and overlapping the 1-1 channel region, the second gate electrode further including a fourth portion overlapping the 2-1 channel region of each of the plurality of second semiconductor pattern layers.
In addition, the closet prior arts teach, discloses a display panel comprising: a base layer including a display region and a non-display region disposed adjacent to the display region; a plurality of insulation layers disposed on the non-display region; a pixel circuit disposed on the display; a light emitting element disposed on the display region, and electrically connected to the pixel circuit; a scan driving circuit disposed on the non-display region, the scan driving circuit and including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor, wherein the first transistor includes: a first semiconductor pattern layer including: a first input region, a first output region, and a first channel region disposed between the first input region and the first output region; a first gate electrode disposed on the first semiconductor pattern layer and overlapping the first channel region; a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including: a second input region electrically connected to the first input region through a first contact hole, a second output region electrically connected to the first output region through a second contact hole, and a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, but fail to teach a shielding electrode disposed on the non-display region the first channel region overlapping the shielding electrode; a first gate electrode overlapping each of the first channel region and the shielding electrode; in a view perpendicular to an upper surface of a base layer, the shield electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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