DETAILED ACTION
This action is responsive to the response filed 27 Feb 2025 and the Information Disclosure Statement filed 27 Feb 2025, 8 Oct 2025 and 23 Feb 2026. Claims 1-20 are pending. Claims 1, 16 and 20 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 27 Feb 2025, 8 Oct 2025 and 23 Feb 2026 are acknowledged. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification: Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Specifically the title should incorporate the nature of the invention which includes generating row hammer adjacent addresses for refresh operations.
Allowable Subject Matter
Claim(s) 3 – 13, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In particular claim 3 requires that the random number generated be used to identify a set of target row addresses and then the activation commands be counted as an integer multiple of the random number while increasing the “count data” for the latched target row addresses.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 16, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho, et al, U.S. Patent Application Publication 2026/0171135 as a proxy for Korean Patent Application Publication 2026/0096291 with a priority date of 17 Dec 2024. (“Cho”).
Regarding claim 1, Cho teaches:
A memory system, comprising: a controller; and a memory device coupled to the controller, wherein the memory device comprises a plurality of memory cell rows, and each of the memory cell rows comprises a plurality of memory cells; wherein the controller is configured to: (Cho, fig 1, 2, 3, “[0035] Referring to FIG. 3, a memory device 200 according to an example embodiment, may include a cell region in which a plurality of memory banks 210 are disposed, and a peripheral circuit region 220. Each of the plurality of memory banks 210 may include a memory cell array 211, a row decoder 212, a sense amplifier circuit 213, and a column decoder 214. The plurality of memory cells included in the memory cell array 211 may be connected to the row decoder 212 through a plurality of wordlines.”; a memory controller, a memory array with memory cells accessible through a plurality of rows or wordlines).
determine one row address among a plurality of buffered row addresses as a row hammer address based on count data corresponding to respective row addresses among the plurality of buffered row addresses; (Cho, fig 6, 7, “[0063] Referring to FIG. 7, a row hammer management circuit 600 may include a queue controller 610 and a queue register 630. … The queue register 630 may include at least one queue to store an address of the candidate aggressor rows and the count data of each of the candidate aggressor rows as count data. [0055] Referring to FIG. 6, a portion of memory cells included in a plurality of memory cell rows, which are count cells, may store count data 500. … Whenever a memory cell row is accessed, the PRAC count value PRAC CNT of the memory cell row may be increased by 1.”; a row counter that counts the number of times any memory row has been accessed as a “candidate aggressor row”).
generate an adjacent row address adjacent to the row hammer address based on the row hammer address, (Cho, fig 7, 9, 10, “[0059] In this case, when the PRAC count value PRAC CNT is 256 or more, that is, when the monitoring count value monitoring CNT is greater than 0, the access row may be a target of management as a candidate aggressor row. [0073] The hammer address storage portion 740 may store the row hammer address HADDR provided from the row hammer management circuit. The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that adjacent rows to the HADDR can be identified and their addresses generated, the HREF ADDR by a Hammer Refresh Address Generator 730 of fig 9).
wherein a target memory cell row to which the adjacent row address points is adjacent to a memory cell row to which the row hammer address points; and (Cho, fig 7, 9, 10, “[0073] The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that the target memory cell row to be refreshed (HREF_ADDR) can be selected by the HREF Address Generator 730, that the target HREF_ADDR can be adjacent to the HADDR).
send the adjacent row address and a row hammer refresh operation command to the memory device, (Cho, fig 7, 9, 10, “[0074] The refresh address generator 760 may receive a normal refresh address NREF ADDR from the normal refresh count 720 and a hammer refresh address HREF ADDR from the hammer refresh address generator.”; the adjacent rows are sent from 730 to the refresh address generator 760 which sends the refresh addresses to the memory array).
wherein the row hammer refresh operation command is configured to instruct to perform a row hammer refresh operation on the target memory cell row. (Cho, fig 9, 10, 11, “[0081] The refresh operation N-REF and F-REF may be performed as a normal refresh operation N-REF or a row hammer refresh operation F-REF depending on whether a candidate row hammer address is stored in the queue. [0082] At the third time point t3, the refresh control logic may determine that it may be necessary to manage the candidate aggressor row and an RFM command may be transmitted to the memory device. [0083] In this case, the memory device may stop the row access operation and may perform the row hammer refresh operation F-REF.”; a hammer refresh operation, an RFM signal is sent to the device based on a count reached at T2, the request is received at the controllers at T3, and the adjacent rows (HREF ADDR) are refreshed at T4).
Regarding claim 16, Cho teaches:
A method of operating a memory system, comprising: (Cho, fig 1, 2, 3, “[0035] Referring to FIG. 3, a memory device 200 according to an example embodiment, may include a cell region in which a plurality of memory banks 210 are disposed, and a peripheral circuit region 220. Each of the plurality of memory banks 210 may include a memory cell array 211, a row decoder 212, a sense amplifier circuit 213, and a column decoder 214. The plurality of memory cells included in the memory cell array 211 may be connected to the row decoder 212 through a plurality of wordlines.”; a memory controller, a memory array with memory cells accessible through a plurality of rows or wordlines).
determining one row address among a plurality of buffered row addresses as a row hammer address based on count data corresponding to respective row addresses among the plurality of buffered row addresses; (Cho, fig 6, 7, “[0063] Referring to FIG. 7, a row hammer management circuit 600 may include a queue controller 610 and a queue register 630. … The queue register 630 may include at least one queue to store an address of the candidate aggressor rows and the count data of each of the candidate aggressor rows as count data. [0055] Referring to FIG. 6, a portion of memory cells included in a plurality of memory cell rows, which are count cells, may store count data 500. … Whenever a memory cell row is accessed, the PRAC count value PRAC CNT of the memory cell row may be increased by 1.”; a row counter that counts the number of times any memory row has been accessed as a “candidate aggressor row”).
generating an adjacent row address adjacent to the row hammer address based on the row hammer address, (Cho, fig 7, 9, 10, “[0059] In this case, when the PRAC count value PRAC CNT is 256 or more, that is, when the monitoring count value monitoring CNT is greater than 0, the access row may be a target of management as a candidate aggressor row. [0073] The hammer address storage portion 740 may store the row hammer address HADDR provided from the row hammer management circuit. The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that adjacent rows to the HADDR can be identified and their addresses generated, the HREF ADDR by a Hammer Refresh Address Generator 730 of fig 9).
wherein a target memory cell row to which the adjacent row address points is adjacent to a memory cell row to which the row hammer address points; and (Cho, fig 7, 9, 10, “[0073] The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that the target memory cell row to be refreshed (HREF_ADDR) can be selected by the HREF Address Generator 730, that the target HREF_ADDR can be adjacent to the HADDR).
sending the adjacent row address and a row hammer refresh operation command to a memory device in the memory system, (Cho, fig 7, 9, 10, “[0074] The refresh address generator 760 may receive a normal refresh address NREF ADDR from the normal refresh count 720 and a hammer refresh address HREF ADDR from the hammer refresh address generator.”; the adjacent rows are sent from 730 to the refresh address generator 760 which sends the refresh addresses to the memory array).
wherein the row hammer refresh operation command is configured to instruct to perform a row hammer refresh operation on the target memory cell row among a plurality of memory cell rows of the memory device. (Cho, fig 9, 10, 11, “[0081] The refresh operation N-REF and F-REF may be performed as a normal refresh operation N-REF or a row hammer refresh operation F-REF depending on whether a candidate row hammer address is stored in the queue. [0082] At the third time point t3, the refresh control logic may determine that it may be necessary to manage the candidate aggressor row and an RFM command may be transmitted to the memory device. [0083] In this case, the memory device may stop the row access operation and may perform the row hammer refresh operation F-REF.”; a hammer refresh operation, an RFM signal is sent to the device based on a count reached at T2, the request is received at the controllers at T3, and the adjacent rows (HREF ADDR) are refreshed at T4).
Regarding claim 20, Cho teaches:
A controller, comprising: at least one circuit configured to: … wherein the controller is coupled to a memory device comprising a plurality of memory cell rows, and wherein each of the memory cell rows comprises a plurality of memory cells. (Cho, fig 1, 2, 3, “[0035] Referring to FIG. 3, a memory device 200 according to an example embodiment, may include a cell region in which a plurality of memory banks 210 are disposed, and a peripheral circuit region 220. Each of the plurality of memory banks 210 may include a memory cell array 211, a row decoder 212, a sense amplifier circuit 213, and a column decoder 214. The plurality of memory cells included in the memory cell array 211 may be connected to the row decoder 212 through a plurality of wordlines.”; a memory controller, a memory array with memory cells accessible through a plurality of rows or wordlines).
determine one row address among a plurality of buffered row addresses as a row hammer address based on count data corresponding to respective row addresses among the plurality of buffered row addresses; (Cho, fig 6, 7, “[0063] Referring to FIG. 7, a row hammer management circuit 600 may include a queue controller 610 and a queue register 630. … The queue register 630 may include at least one queue to store an address of the candidate aggressor rows and the count data of each of the candidate aggressor rows as count data. [0055] Referring to FIG. 6, a portion of memory cells included in a plurality of memory cell rows, which are count cells, may store count data 500. … Whenever a memory cell row is accessed, the PRAC count value PRAC CNT of the memory cell row may be increased by 1.”; a row counter that counts the number of times any memory row has been accessed as a “candidate aggressor row”).
generate an adjacent row address adjacent to the row hammer address based on the row hammer address, (Cho, fig 7, 9, 10, “[0059] In this case, when the PRAC count value PRAC CNT is 256 or more, that is, when the monitoring count value monitoring CNT is greater than 0, the access row may be a target of management as a candidate aggressor row. [0073] The hammer address storage portion 740 may store the row hammer address HADDR provided from the row hammer management circuit. The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that adjacent rows to the HADDR can be identified and their addresses generated, the HREF ADDR by a Hammer Refresh Address Generator 730 of fig 9).
wherein a target memory cell row to which the adjacent row address points is adjacent to a memory cell row to which the row hammer address points; and (Cho, fig 7, 9, 10, “[0073] The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that the target memory cell row to be refreshed (HREF_ADDR) can be selected by the HREF Address Generator 730, that the target HREF_ADDR can be adjacent to the HADDR).
send the adjacent row address and a row hammer refresh operation command to the memory device, (Cho, fig 7, 9, 10, “[0074] The refresh address generator 760 may receive a normal refresh address NREF ADDR from the normal refresh count 720 and a hammer refresh address HREF ADDR from the hammer refresh address generator.”; the adjacent rows are sent from 730 to the refresh address generator 760 which sends the refresh addresses to the memory array).
wherein the row hammer refresh operation command is configured to instruct to perform a row hammer refresh operation on the target memory cell row, (Cho, fig 9, 10, 11, “[0081] The refresh operation N-REF and F-REF may be performed as a normal refresh operation N-REF or a row hammer refresh operation F-REF depending on whether a candidate row hammer address is stored in the queue. [0082] At the third time point t3, the refresh control logic may determine that it may be necessary to manage the candidate aggressor row and an RFM command may be transmitted to the memory device. [0083] In this case, the memory device may stop the row access operation and may perform the row hammer refresh operation F-REF.”; a hammer refresh operation, an RFM signal is sent to the device based on a count reached at T2, the request is received at the controllers at T3, and the adjacent rows (HREF ADDR) are refreshed at T4).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Kim, et al, U.S. Patent Application Publication 20250103217 (“Kim”).
Regarding claim 2, Cho teaches the memory system of claim 1.
Cho teaches:
wherein the controller is further configured to: send a plurality of activation commands to the memory device, (Cho, fig 8, 9, “[0064] Referring to FIG. 8, each queue may include a bank register B_REGl-B_REGn configured to store the address of each memory bank.”; that a queue can be established with multiple addresses for refresh).
wherein one of the activation commands is configured to instruct to activate one target row address; and (Cho, fig 8, 9, 11, “[0063] The queue register 630 may store information about candidate aggressor rows intensively accessed among access rows. The queue register 630 may include at least one queue to store an address of the candidate aggressor rows and the count data of each of the candidate aggressor rows as count data. [0064] A queue may be a storage space implemented with a flip-flop, a latch, a buffer circuit, a static random access memory (SRAM), or the like, and may operate in a first-in-first-out (FIFO) manner.”; that each of the queues can be refreshed on a FIFO basis via activation commands to the memory during the time slots of fig 11).
Cho does not explicitly teach randomly latch the target row address corresponding to at least one of the activation commands based on a generated random number..
Kim teaches randomly latch the target row address corresponding to at least one of the activation commands based on a generated random number. (Kim, fig 2, 3, “[0057] Referring to FIG. 3, the row hammer control circuit 140 may include a random number generator 141, a memory cell row picking circuit 142A, and a memory cell row picking circuit 142B. When the enable signal RPC1_EN is applied to the memory cell row picking circuit 142A, the memory cell row picking circuit 142A may randomly select one memory cell row among the plurality of memory cell rows of the memory cell array 110 (shown in FIG. 2), on the basis of the received n-bit pseudo random bit sequence signal PRBS1. At this time, the memory cell row selected by the memory cell row picking circuit 142A may be a target row that is intensively accessed during the row hammer monitoring time interval of the control logic circuit 130,”; that rather than FIFO, the refresh order for the victim rows can be randomly selected).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Cho before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Kim, in the same or in a similar field of endeavor with Cho, can combine Kim’s random selection of refresh row hammer addresses and Cho’s First In- First Out selection of refresh row hammer addresses The two methods for generating and selecting row hammer refresh addresses merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, Cho teaches the memory system of claim 1.
Cho does not explicitly teach wherein the memory device comprises a dynamic random access memory..
Kim teaches wherein the memory device comprises a dynamic random access memory. (Kim, fig 1, “[0040] As an example, the memory device 100 may be provided as a random access memory (RAM) device, such as a Dynamic Random Access Memory (DRAM), a Synchronous DRAM (SDRAM),…”; that row hammer operations can be performed on DRAM circuits).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Cho before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Kim, in the same or in a similar field of endeavor with Cho, can combine Kim’s random selection of refresh row hammer addresses and Cho’s First In- First Out selection of refresh row hammer addresses The two methods for generating and selecting row hammer refresh addresses merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 17, Cho teaches the method of claim 16.
Cho teaches:
further comprising: sending a plurality of activation commands to the memory device, (Cho, fig 8, 9, “[0064] Referring to FIG. 8, each queue may include a bank register B_REGl-B_REGn configured to store the address of each memory bank.”; that a queue can be established with multiple addresses for refresh).
wherein one of the activation commands is configured to instruct to activate one target row address; and (Cho, fig 8, 9, 11, “[0063] The queue register 630 may store information about candidate aggressor rows intensively accessed among access rows. The queue register 630 may include at least one queue to store an address of the candidate aggressor rows and the count data of each of the candidate aggressor rows as count data. [0064] A queue may be a storage space implemented with a flip-flop, a latch, a buffer circuit, a static random access memory (SRAM), or the like, and may operate in a first-in-first-out (FIFO) manner.”; that each of the queues can be refreshed on a FIFO basis via activation commands to the memory during the time slots of fig 11).
Cho does not explicitly teach randomly latching the target row address corresponding to at least one of the activation commands based on a generated random number..
Kim teaches randomly latching the target row address corresponding to at least one of the activation commands based on a generated random number. (Kim, fig 2, 3, “[0057] Referring to FIG. 3, the row hammer control circuit 140 may include a random number generator 141, a memory cell row picking circuit 142A, and a memory cell row picking circuit 142B. When the enable signal RPC1_EN is applied to the memory cell row picking circuit 142A, the memory cell row picking circuit 142A may randomly select one memory cell row among the plurality of memory cell rows of the memory cell array 110 (shown in FIG. 2), on the basis of the received n-bit pseudo random bit sequence signal PRBS1. At this time, the memory cell row selected by the memory cell row picking circuit 142A may be a target row that is intensively accessed during the row hammer monitoring time interval of the control logic circuit 130,”; that rather than FIFO, the refresh order for the victim rows can be randomly selected).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Cho before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Kim, in the same or in a similar field of endeavor with Cho, can combine Kim’s random selection of refresh row hammer addresses and Cho’s First In- First Out selection of refresh row hammer addresses The two methods for generating and selecting row hammer refresh addresses merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Ito, et al, U.S. Patent 11,417,385 (“Ito”).
Cho teaches the memory system of claim 1.
Cho teaches:
wherein the row hammer refresh operation command comprises a row hammer activation command and a pre-charge command; (Cho, fig 3, “[0038] Additionally, the memory controller 200 may control memory operations, such as writing and reading, by providing various signals to the memory device 100 through the device interface 230. For example, the memory controller 200 may provide a pre-charge command to the memory device 100. The pre-charge command may be a command for switching the state of the memory cell array 110 from an active state to a standby state after writing or reading is completed. [0039] According to some embodiments, when the memory controller 200 provides an access command to the memory device 100, the address ADDR of the row to be accessed may be sent to the memory device 100 along with the access command.”; that a precharge operation is typically part of the address selection process to enable a “write” operation, note: a “refresh” operation is considered to be a “write” operation).
the row hammer activation command is configured to instruct to perform an activation operation on the row address corresponding to the target memory cell row; and (Cho, fig 7, 9, 10, “[0059] In this case, when the PRAC count value PRAC CNT is 256 or more, that is, when the monitoring count value monitoring CNT is greater than 0, the access row may be a target of management as a candidate aggressor row. [0073] The hammer address storage portion 740 may store the row hammer address HADDR provided from the row hammer management circuit. The mapping portion 750 may output a row hammer refresh address HREF _ADDR based on a hammer address HADDR provided from the hammer address storage portion 740. The row hammer refresh address HREF ADDR may be an address of a row physically adjacent to a row corresponding to the row hammer address HADDR.”; that adjacent rows to the HADDR can be generated by a Hammer Refresh Address Generator 730 of fig 9, that the command is an instruction to hammer refresh the target addressed rows).
Cho does not explicitly teach the pre-charge command is configured to instruct to perform a pre-charge operation on a column address corresponding to a selected memory cell among the plurality of memory cells in the target memory cell row..
Ito teaches the pre-charge command is configured to instruct to perform a pre-charge operation on a column address corresponding to a selected memory cell among the plurality of memory cells in the target memory cell row. (Ito, fig 14, “(145) An RHR thinning circuit 1220 is coupled to the RHRSLOT generating circuit 1210. The RHR thinning circuit 1220 generates the second refresh signal RHRSLOT according to the third refresh signal RHRSLOTPre, the active signal ACT of the corresponding memory block, and the pre-charge signal PREC. It should be noted that the pre-charge signal PREC is, for example, a pulse signal generated when a bit line is about to be pre-charged.”; that a precharge operation is typically directed to the bitline or column when starting an Row Hammer Refresh (HMR) operation).
In view of the teachings of Ito it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ito to Cho before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Ito, in the same or in a similar field of endeavor with Cho, can combine Ito’s more explicit column precharge operation with Cho’s more general precharge operations. The two methods for precharging row hammer refresh addresses merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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