Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 8, 10, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US 2022/0351802), in view of Cao et al. (US 12,322,445), hereinafter Cao, further in view of Varlan et al. (US 2025/0355042), hereinafter Varlan, and further in view of Toshima (US 10,114,065).
Regarding claim 1, Shi teaches a non-volatile memory device comprising: a cell array comprising memory cells connected to a word line (Shi, Abstract, lines 1-4, “A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line”);
a voltage generator configured to generate a word line voltage and provide the word line voltage to the word line (Shi, Abstract, lines 4-6, “a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line”); and
a bonding defect detection circuit connected to a first node (Shi, Fig. 2 teaches a word line leakage detection circuit coupled to a selected word line through a coupling circuit that includes a switch, an isolation capacitor, and a detector receiving a voltage associated with the selected word line), and configured to detect a voltage level of the first node in a precharge section of the word line or in a development section of the word line (Shi, Fig. 7 teaches providing a preset voltage from a driving voltage source, to a selected word line, disconnecting the selected word line from the source, and after a preset time, detecting the voltage at the coupling circuit, and determining abnormal leakage from the detected voltage; para. [0015], lines 1-4, “In some implementations, after disconnecting the selected word line and the driving voltage source, the method further includes setting the selected word line to a floating status”; this floating state can equate to a development section),
wherein the bonding defect detection circuit is further configured to:
detect a discharge speed of the word line that has been precharged in the development section (Shi teaches charging a selected word line to a first preset voltage, disconnecting it from a driving voltage source, placing it in a floating status, waiting a preset time, and detecting its resulting voltage change).
Shi fails to teach a word line bonding configured to electrically connect the voltage generator and the word line, a bonding defect detection circuit connected to a first node between the voltage generator and the word line bonding, detecting a voltage level of the first node in a precharge or development section in order to determine whether there is a defect in the word line bonding, detect a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect, and detecting a discharge speed of the word line that has been precharged in the development section in order to identify a short defect in the word line bonding.
However, Cao, in an analogous art, teaches a word line bonding configured to electrically connect the voltage generator and the word line (Cao, col. 1, lines 35-67 through col. 2, lines 1-16 describe a memory-array unit having word lines, a peripheral-drive-circuit unit, word line bonding regions, substrate-connecting bonding regions electrically coupled to the peripheral-drive-circuit unit and connected to respective word lines), a bonding defect detection circuit connected to a first node (Shi’s Fig. 2 teaches a bonding defect detection circuit structure) between the voltage generator and the word line bonding (Cao teaches placing a bonded interface in the path between the peripheral-drive circuitry and word line; this teaching, combined with Shi’s monitoring circuit being applied to Cao’s bonded word line path, would result in the monitored node being positioned on the voltage generator side of the bonded path), detecting a voltage level of the first node in a precharge or development section in order to determine whether there is a defect in the word line bonding (Cao teaches placing bonding contacts in the word line path; this teaching, combined with applying Shi’s electrical monitoring to that path, would result in detecting an abnormal electrical condition caused by a defective bonded connection), and detecting a discharge speed of the word line that has been precharged in the development section in order to identify a short defect in the word line bonding (Cao teaches the word line bonding structure, as well as an unintended conductive path at or associated with the bonded connections causing some sort of abnormal discharge of a word line path; this teaching, combined with Shi’s teaching of detecting abnormal leakage between a selected word line and an adjacent word line or a selected word line and a bit line, and then comparing a detected voltage difference with a threshold, and classifying whether a leakage state is abnormal, teaches identifying a short defect in the word line bonding).
Shi and Cao are both considered to be analogous to the claimed invention because both are in the same field of semiconductor 3D memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Shi’s word line driving and leakage detection circuitry to incorporate the teachings of Cao by including the functionality of having a bonded architecture that includes connecting peripheral driving circuitry to word lines through bonded conductive regions.
The suggestion/motivation for doing so would be that it would provide a compact memory structure while still allowing for word line voltage driving and monitoring functionality.
The combination of Shi in view of Cao, taken singly or combined, fail to teach detect a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect.
However, Varlan, in an analogous art, teaches detect a precharge speed of the word line in the precharge section (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval; this teaching, combined with Shi supplying the word line that is charged, teaches a mechanism for converting the charging response into a measurement that represents a time when a threshold was reached/crossed).
Shi, Cao, and Varlan are considered to be analogous to the claimed invention because they are in the same field of circuitry within semiconductor memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of providing a measurement of a charging response.
The suggestion/motivation for doing so would be that using the functionality taught in Varlan with Shi’s selected word line would provide a way to quantify the word line precharge response instead of simply observing the voltage at a fixed time.
The combination of Shi in view of Cao, further in view of Varlan, taken singly or combined, fail to teach detecting a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect.
However, Toshima, in an analogous art, teaches detecting a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect (Toshima, Abstract, lines 5-9, “determining a presence of a high resistance defect in the conductive structure based on at least one of a delay of a rising edge of the alternating current waveform and a decrease in amplitude of the alternating current waveform”; this teaching, combined with Shi in view of Cao’s teaching of a bonded word-line path and charge response measurement, teaches the limitation).
Shi, Cao, Varlan, and Toshima are considered to be analogous to the claimed invention because they are in the same field of semiconductor integrated circuits that utilize voltage monitoring and electrical defect detection.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao, further in view of Varlan, to incorporate the teachings of Toshima by including the functionality of identifying a resistive defect.
The suggestion/motivation for doing so would be to allow for a resistive defect to be identified when a measured precharge interval exceeds a reference voltage range.
Regarding claim 2, the combination of Shi, in view of Cao, further in view of Varlan, and further in view Toshima, teaches the non-volatile memory device of claim 1, wherein the bonding defect detection circuit comprises: a comparator configured to compare the voltage level of the first node with a reference voltage; a counter configured to perform a counting operation based on a first enable signal and reset based on a second enable signal (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval); a register configured to latch a count output of the counter based on an output of the comparator and output the count output as a detection count (Varlan does not explicitly teach a register, however the counter would most likely need to retain counts after the stop signal); and a decision circuit configured to determine a defect type of the word line bonding based on the detection count (Varlan’s teaching of providing a time measurement of a charging response, combined with Shi’s teaching of identifying defects based on electrical behavior of a word line, teaches the limitation).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of storing measured counts to registers and comparison circuitry.
The suggestion/motivation for doing so would be to retain the counts and compare them to stored criteria for defect classification.
Regarding claim 3, the combination of Shi, in view of Cao, further in view of Varlan, and further in view Toshima, teaches the non-volatile memory device of claim 2, wherein the register is configured to: latch the count output based on the voltage level of the first node becoming higher than the reference voltage in the precharge section, and latch the count output based on the voltage level of the first node becoming lower than the reference voltage (Varlan teaches stopping a counter when the rising ramp reaches or exceeds the reference voltage) in the development section (Shi, Fig. 7 teaches providing a preset voltage from a driving voltage source, to a selected word line, disconnecting the selected word line from the source, and after a preset time, detecting the voltage at the coupling circuit, and determining abnormal leakage from the detected voltage; para. [0015], lines 1-4, “In some implementations, after disconnecting the selected word line and the driving voltage source, the method further includes setting the selected word line to a floating status”; this floating state can equate to a development section).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of latch8ing count outputs based on voltage levels compared to reference voltages.
The suggestion/motivation for doing so would be to retain the counts no matter how they compare to the reference voltages.
Regarding claim 8, the combination of Shi, in view of Cao, further in view of Varlan, and further in view Toshima, teaches the non-volatile memory device of claim 2, further comprising: a power switch configured to transmit the word line voltage to the first node based on a third enable signal (Shi, para. [0005], lines 10-13, “the coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit”).
Regarding claim 10, Shi teaches a method of detecting bonding defect a non-volatile memory device (Shi, Abstract, lines 1-4, “A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line”) that transmits a word line voltage generated by a voltage generator to a word line of a cell array (Shi, Abstract, lines 4-6, “a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line).
Shi fails to teach transmitting a word line voltage generated by a voltage generator to a word line of a cell array through a word line bonding, precharging the word line with the word line voltage; counting a first time when a voltage level of the word line becomes higher than a reference voltage from a time of precharge using a counter to generate a first detection count; and identifying a bonding defect of the word line based on the first detection count, wherein the bonding defect is an open defect or a resistive defect.
However, Cao, in an analogous art, teaches transmitting a word line voltage generated by a voltage generator to a word line of a cell array through a word line bonding (Cao, col. 1, lines 35-67 through col. 2, lines 1-16 describe a memory-array unit having word lines, a peripheral-drive-circuit unit, word line bonding regions, substrate-connecting bonding regions electrically coupled to the peripheral-drive-circuit unit and connected to respective word lines).
Shi and Cao are both considered to be analogous to the claimed invention because both are in the same field of semiconductor 3D memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Shi to incorporate the teachings of Cao by including the functionality of having a bonded architecture that includes transmitting word line voltages through bonded conductive regions.
The suggestion/motivation for doing so would be that it would provide a compact memory structure while still allowing for word line voltage driving and monitoring functionality.
The combination of Shi in view of Cao, taken singly or combined, fail to teach precharging the word line with the word line voltage; counting a first time when a voltage level of the word line becomes higher than a reference voltage from a time of precharge using a counter to generate a first detection count; and identifying a bonding defect of the word line based on the first detection count, wherein the bonding defect is an open defect or a resistive defect.
However, Varlan, in an analogous art, teaches precharging the word line with the word line voltage; counting a first time when a voltage level of the word line becomes higher than a reference voltage from a time of precharge using a counter to generate a first detection count (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval; this teaching, combined with Shi supplying the word line that is charged, teaches a mechanism for converting the charging response into a measurement that represents a time when a threshold was reached/crossed); and identifying a bonding defect of the word line based on the first detection count (Varlan’s teaching of providing a time measurement of a charging response, combined with Shi’s teaching of identifying defects based on electrical behavior of a word line, teaches the limitation).
Shi, Cao, and Varlan are considered to be analogous to the claimed invention because they are in the same field of circuitry within semiconductor memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of providing a measurement of an elapsed charging interval of a voltage node using a comparator, reference voltage, and a counter.
The suggestion/motivation for doing so would be that using the functionality taught in Varlan with Shi’s selected word line would provide a way to quantify the word line precharge response in a way that is useful for comparison and defect evaluation.
The combination of Shi in view of Cao, further in view of Varlan, taken singly or combined, fail to teach wherein the bonding defect is an open defect or a resistive defect.
However, Toshima, in an analogous art, teaches wherein the bonding defect is an open defect or a resistive defect (Toshima, Abstract, lines 5-9, “determining a presence of a high resistance defect in the conductive structure based on at least one of a delay of a rising edge of the alternating current waveform and a decrease in amplitude of the alternating current waveform”; this teaching, combined with Shi in view of Cao’s teaching of a bonded word-line path and charge response measurement, teaches the limitation).
Shi, Cao, Varlan, and Toshima are considered to be analogous to the claimed invention because they are in the same field of semiconductor integrated circuits that utilize voltage monitoring and electrical defect detection.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao, further in view of Varlan, to incorporate the teachings of Toshima by including the functionality of identifying a resistive defect.
The suggestion/motivation for doing so would be to allow for a resistive defect to be identified when a measured precharge interval exceeds a reference voltage range.
Regarding claim 14, the combination of Shi, in view of Cao, further in view of Varlan, and further in view Toshima, teaches the method of claim 10, further comprising: resetting the counter (Varlan, para. [0023], lines 14-16, “When receiving the self-test enable signal and the start signal, the time evaluation circuit 114 may be reset. Thus, as an example, the counter may start counting up again from 0”); electrically separating the word line precharged with the word line voltage from the voltage generator (Shi, para. [0015], lines 1-4, “In some implementations, after disconnecting the selected word line and the driving voltage source, the method further includes setting the selected word line to a floating status”); counting a second time when a development level of the word line becomes lower than the reference voltage to generate a second detection count (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval); and identifying the bonding defect of the word line based on the second detection count, wherein the bonding defect identified based on the second detection count is a short defect (Shi teaches detecting abnormal leakage between a selected word line and an adjacent word line or a selected word line and a bit line, and then comparing a detected voltage difference with a threshold, and classifying whether a leakage state is abnormal).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of counter-based threshold timing.
The suggestion/motivation for doing so would be generate a second count and have the ability to identify a leakage/short defect.
Regarding claim 15, the combination of Shi, in view of Cao, further in view of Varlan, and further in view Toshima, teaches the method of claim 14, wherein the short defect does not exist when the development level of the word line becoming lower than the reference voltage does not occur (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval). Shi teaches that an abnormal leakage results only if the difference between a reference voltage and a rising voltage reaches or exceeds a threshold. If the difference remains under the threshold, no abnormal leakage result is produced.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cao, in view of Shi, further in view of Varlan, and further in view of Toshima.
Regarding claim 16, Cao teaches a non-volatile memory device (Cao, col. 1, lines 35-36, “A semiconductor structure is provided according to embodiments of the present disclosure”) comprising: a word line bonding configured to electrically connect the voltage generator and the word line (Cao, col. 1, lines 35-67 through col. 2, lines 1-16 describe a memory-array unit having word lines, a peripheral-drive-circuit unit, word line bonding regions, substrate-connecting bonding regions electrically coupled to the peripheral-drive-circuit unit and connected to respective word lines); and identifying a short defect of the word line bonding (Cao teaches the word line bonding structure, as well as an unintended conductive path at or associated with the bonded connections causing some sort of abnormal discharge of a word line path).
Cao fails to teach memory cells connected to a word line; a voltage generator configured to generate a word line voltage and provide the word line voltage to the word line, a voltage drop circuit connected to a first node between the voltage generator and the word line bonding to drop a level of the word line voltage and provide a dropped word line voltage as a detection voltage to a second node; and a bonding defect detection circuit configured to detect a level of the detection voltage in a precharge section of the word line or in a development section of the word line to determine whether the word line bonding is defective, wherein the bonding defect detection circuit is further configured to: detect a precharge speed of the word line in the precharge section based on the level of the detection voltage to identify an open defect or a resistive defect, and detect a discharge speed of the word line that has been precharged in the development section to identify a short defect of the word line bonding.
However, Shi teaches memory cells connected to a word line (Shi, Abstract, lines 1-4, “A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line”); a voltage generator configured to generate a word line voltage and provide the word line voltage to the word line (Shi, Abstract, lines 4-6, “a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line”), a voltage drop circuit connected to a first node between the voltage generator and the word line bonding to drop a level of the word line voltage and provide a dropped word line voltage as a detection voltage to a second node (Shi, Fig. 7, Abstract, lines 6-13, “at least one word line leakage detection circuit, configured to detect a leakage state of the selected word line; and at least one coupling circuit corresponding to the word line leakage detection circuit. The coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit, and the isolation capacitor is used for isolating the word line leakage detection circuit and the word line driving circuit”); and a bonding defect detection circuit (Shi, Fig. 2 teaches a word line leakage detection circuit coupled to a selected word line through a coupling circuit that includes a switch, an isolation capacitor, and a detector receiving a voltage associated with the selected word line) configured to detect a level of the detection voltage in a precharge section of the word line or in a development section of the word line (Shi, Fig. 7 teaches providing a preset voltage from a driving voltage source, to a selected word line, disconnecting the selected word line from the source, and after a preset time, detecting the voltage at the coupling circuit, and determining abnormal leakage from the detected voltage; para. [0015], lines 1-4, “In some implementations, after disconnecting the selected word line and the driving voltage source, the method further includes setting the selected word line to a floating status”; this floating state can equate to a development section) to determine whether the word line bonding is defective (Shi teaches the electrical monitoring of a word line; this teaching, combined with Cao’s teaching of placing bonding contacts in the word line, would result in detecting an abnormal electrical condition caused by a defective bonded connection) , and detect a discharge speed of the word line that has been precharged in the development section to identify a short defect of the word line bonding (Shi teaches determining leakage after the floating state, as well as an abnormal leaking path).
Cao and Shi are both considered to be analogous to the claimed invention because both are in the same field of semiconductor 3D memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Cao’s bonded memory architecture to incorporate the teachings of Shi’s word line charging, floating, and voltage monitoring techniques.
The suggestion/motivation for doing so would have enabled electrical evaluation of the bonded word line path, while maintaining the bonding architecture.
The combination of Cao in view of Shi, taken singly or combined, fail to teach detect a precharge speed of the word line in the precharge section based on the level of the detection voltage to identify an open defect or a resistive defect.
However, Varlan, teaches detect a precharge speed of the word line in the precharge section based on the level of the detection voltage (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval; this teaching, combined with Shi supplying the word line that is charged, teaches a mechanism for converting the charging response into a measurement that represents a time when a threshold was reached/crossed).
Cao, Shi, and Varlan are considered to be analogous to the claimed invention because they are in the same field of circuitry within semiconductor memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Cao in view of Shi to incorporate the teachings of Varlan by including the functionality of providing a measurement of a charging response.
The suggestion/motivation for doing so would be that using the functionality taught in Varlan with Shi’s selected word line would provide a way to quantify the word line precharge response instead of simply observing the voltage at a fixed time.
The combination of Cao in view of Shi, further in view of Varlan, taken singly or combined, fail to teach detecting a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect.
However, Toshima, teaches detecting a precharge speed of the word line in the precharge section to identify an open defect or a resistive defect (Toshima, Abstract, lines 5-9, “determining a presence of a high resistance defect in the conductive structure based on at least one of a delay of a rising edge of the alternating current waveform and a decrease in amplitude of the alternating current waveform”; this teaching, combined with Shi in view of Cao’s teaching of a bonded word-line path and charge response measurement, teaches the limitation).
Cao, Shi, Varlan, and Toshima are considered to be analogous to the claimed invention because they are in the same field of semiconductor integrated circuits that utilize voltage monitoring and electrical defect detection.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Cao in view of Shi, further in view of Varlan, to incorporate the teachings of Toshima by including the functionality of identifying a resistive defect.
The suggestion/motivation for doing so would be to allow for a resistive defect to be identified when a measured precharge interval exceeds a reference voltage range.
Regarding claim 17, the combination of Cao, in view of Shi, further in view of Varlan, and further in view of Toshima, teaches the non-volatile memory device of claim 16, wherein the bonding defect detection circuit comprises: a comparator configured to compare the detection voltage with a reference voltage; a counter performing a counting operation based on a first enable signal and reset based on a second enable signal (Varlan, Fig. 1, para. [0015]-[0018] teaches beginning the generation of a voltage ramp with a start signal, starting a counter with the start signal, continuously comparing the rising voltage with a reference voltage, using the comparator output as a stop signal with the voltage reaches the reference voltage, and stopping the counter so that its count represents the charging interval); a first register configured to latch a count output of the counter based on an output of the comparator at a first time point when the detection voltage becomes higher than the reference voltage in the precharge section, and provide the count output as a first detection count; a second register configured to latch the count output of the counter based on the output of the comparator at a second time point when the detection voltage becomes lower than the reference voltage in the development section, and provide the count output as a second detection count (Varlan does not explicitly teach two registers, however separating two timing values into respective storage locations would have been an obvious implementation choice to retain both measurements for later comparison); and a decision circuit configured to compare the first detection count or the second detection count with a reference value to determine a type of defect in the word line bonding (Varlan’s teaching of providing a time measurement of a charging response, combined with Shi’s teaching of identifying defects based on electrical behavior of a word line, teaches the limitation).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shi in view of Cao to incorporate the teachings of Varlan by including the functionality of storing measured counts to registers and comparison circuitry.
The suggestion/motivation for doing so would be to retain the counts and compare them to stored criteria for defect classification.
Regarding claim 18, the combination of Cao, in view of Shi, further in view of Varlan, and further in view of Toshima, teaches the non-volatile memory device of claim 17, further comprising: a first power switch configured to transmit the word line voltage to the first node based on a third enable signal (Shi, para. [0005], lines 10-13, “the coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit”).
Regarding claim 19, the combination of Cao, in view of Shi, further in view of Varlan, and further in view of Toshima, teaches the non-volatile memory device of claim 18, further comprising: a second power switch configured to initialize the second node to a development start voltage based on the second enable signal when a precharge section ends. Shi does not explicitly teach a second power switch, however initialiazing a detector node before beginning a timing measurement is a conventional initialization step.
Allowable Subject Matter
Claims 4-7, 9, 11-13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kuroda (US 2011/0194345) teaches word-line failure detection and reference voltage comparison.
Boos (US 5,430,383) teaches RC charging behavior of open conductive paths.
Delshadpour et al. (US 10,763,809) teaches voltage detection circuitry.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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