DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed by Applicant on 03/24/2026. This action is made FINAL.
Examiner’s Notes
Regarding claims 1, 4-6, 14-16, and 20, the Examiner respectfully disagrees with Applicant’s comments as would be detailed in the forthcoming action.
Regarding claims 2-3, after reviewing Applicant’s arguments in view of the prior art presented and the claim scope, the subject matter therein is hereby deemed to be allowable.
Applicant’s attention is respectfully drawn to the broad nature of the term “arranged in a first/second direction.” It is understood that the Applicant is referring to DR1 and DR2 of the instant application. However, consider for example figure 2 of Jeong et al, both the scan lines and the pixel rows/columns can be read as extending in both vertical and horizontal axes. In other words, S51-S5n are arranged in one direction and S51-S11 are arranged in a different direction transverse to that direction. Similarly, pixel rows/columns are arranged in two directions transverse to each other. Therefore, the figure 2 of Jeong et al reads upon the broad language of the claimed “arranged in a direction.”
While not relied upon in this response, it is hereby noted that the claims are not worded in a manner that necessarily mean “multiple scan drivers per pixel row” as argued by the Applicant. The claims only mention that the first and second drivers share a clock signal. Such argument can be reserved for later stages of prosecution in case it is necessary.
Response to Arguments
Applicant's arguments filed 03/24/2026 have been fully considered but they are not persuasive.
Applicant states that “Arguendo, JEONG '604's FIG. 2 presents as a conceptual block diagram without axes. Generally, physical layout or arrangement should not be assumed from such a diagram, and the Examiner has not argued otherwise. JEONG '604 do not show an actual layout diagram for a gate driver such as in a plan view with axes. This is to be expected since JEONG '604 was focused on a pixel circuit rather than a gate driver. But even if axes and layout were to be implied to support the Examiner's argument, JEONG '604's purported first stage of first gate driver (210) and second stage of second gate driver (220) would not be arranged in the first direction defined by the arrangement of the plurality of pixel rows, but would instead be arranged in a second direction crossing the first direction.” However, figure 2 of Jeong et al shows that vertical scan lines are arranged in the DR1 (as indicated by the instant application), and pixel columns are arranged in the second direction.
Applicant states that “This is to be expected since JEONG '604 was focused on a pixel circuit rather than a gate driver.” However, Jeong et al specifically shows the scan signals are supplied by the gate drivers. For example, see paragraph 137.
Regarding the limitations of “the first gate driver and the second gate driver share a first clock signal;” see figure 10A where Liu et al shows clock signal ECK3 being connected to ET1 and ET3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (Publication number: US 2023/0140604) in view of Liu et al (Publication number: US 2024/0363066).
Consider Claim 1, Jeong et al shows a display device (see figure 1), comprising:
(a) A display panel including a plurality of pixel rows arranged in a first direction, each pixel row including a plurality of pixels (see figure 2); (See pixel unit 100).
(b) A first gate driver including a first stage having a first gate signal as a first output to each of the plurality of pixel rows (see figure 2); (Read as first scan driver 210).
(c) A second gate driver including a second stage having a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in the first direction (see figure 2; and paragraphs 60-62); (The second gate driver is read as first scan driver 220. Further, the scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
(d) Wherein each of the first stage and the second stage is connected to at least four pixel rows among the plurality of pixel rows (see figure 2; and paragraph 61); (The scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
However, Jeong et al does not specifically show that the first gate driver and the second gate driver share a first clock signal.
In the same field of endeavor, Liu et al shows that the first gate driver and the second gate driver share a first clock signal (see figures 5 and 7; and paragraphs 71-75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan clock signal lines of Liu into the driving circuit of Jeong et al in order to achieve lower power consumption (see Liu et al; paragraph 3).
Consider Claim 15, Jeong et al shows a gate driver (see figure 1), comprising:
(a) A first gate driver including a first stage having a first gate signal as a first output to each of a plurality of pixel rows (see figure 2); (Read as first scan driver 210).
(b) A second gate driver including a second stage having a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in a first direction (see figure 2; and paragraphs 60-62); (The second gate driver is read as first scan driver 220. Further, the scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
(c) Wherein each of the first stage and the second stage is connected to at least four pixel rows among the plurality of pixel rows (see figure 2; and paragraph 61); (The scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
However, Jeong et al does not specifically show that the first gate driver and the second gate driver share a first clock signal.
In the same field of endeavor, Liu et al shows that the first gate driver and the second gate driver share a first clock signal (see figures 5 and 7; and paragraphs 71-75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan clock signal lines of Liu into the driving circuit of Jeong et al in order to achieve lower power consumption (see Liu et al; paragraph 3).
Consider Claim 20, Jeong et al shows an electronic apparatus (see figure 1), comprising:
(a) A processor which generates image data; and a display device which displays an image based on the image data, wherein the display device comprises: a display panel including a plurality of pixel rows arranged in a first direction and each including a plurality of pixels (see figure 2); (See pixel unit 100).
(b) A first gate driver including a first stage having a first gate signal as a first output to each of the plurality of pixel rows (see figure 2); (Read as first scan driver 210).
(c) A second gate driver including a second stage having a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in the first direction (see figure 2; and paragraphs 60-62); (The second gate driver is read as first scan driver 220. Further, the scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
(d) Wherein each of the first stage and the second stage is connected to at least four pixel rows among the plurality of pixel rows (see figure 2; and paragraph 61); (The scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS).
However, Jeong et al does not specifically show that the first gate driver and the second gate driver share a first clock signal.
In the same field of endeavor, Liu et al shows that the first gate driver and the second gate driver share a first clock signal (see figures 5 and 7; and paragraphs 71-75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan clock signal lines of Liu into the driving circuit of Jeong et al in order to achieve lower power consumption (see Liu et al; paragraph 3).
Consider Claims 4 and 16, Jeong et al shows a third gate driver including a third stage having a third gate signal as a third output to each of the plurality of pixel rows (see figure 2); (Read as third scan driver 230); a fourth gate driver including a fourth stage having a fourth gate signal as a fourth output to each of the plurality of pixel rows, the fourth stage being alternately arranged with the third stage in the first direction, wherein each of the third stage and the fourth stage is connected to at least four pixel rows among the plurality of pixel rows (see figure 2; and paragraphs 60-62); (The fourth gate driver is read as first scan driver 240. Further, the scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, fourth scan lines S41 to S4n, and fifth scan lines S51 to S5n, respectively, based on the first control signal SCS);
However, Jeong et al does not specifically show that the third gate driver and the fourth gate driver share a second clock signal.
In the same field of endeavor, Liu et al shows that the third gate driver and the fourth gate driver share a second clock signal (see figures 5 and 7; and paragraphs 71-75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan clock signal lines of Liu into the driving circuit of Jeong et al in order to achieve lower power consumption (see Liu et al; paragraph 3).
Consider Claim 5, Jeong et al shows that the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver are positioned towards a first side of the plurality of pixel rows in a second direction crossing the first direction (see figure 2); (see the positions of first to fifth scan drivers).
Consider Claim 6, Jeong et al shows that the first gate driver and the second gate driver are positioned towards a first side of the plurality of pixel rows in a second direction crossing the first direction, and wherein the third gate driver and the fourth gate driver are positioned towards a second side of the plurality of pixel rows opposite to the first side in the second direction (see figure 2); (see the positions of first to fifth scan drivers).
Consider Claim 14, Jeong et al shows that each of the first stage and the second stage includes a plurality of transistors, and wherein each of the transistors is an N-type oxide semiconductor transistor (see paragraph 62).
Allowable Subject Matter
Claims 2-4, 7-13, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 05/29/2026
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