Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
In response to a restriction requirement dated December 10, 2025 the Applicants elected Invention I of claims 1-12 and 20 without traverse in a reply filed on February 6, 2026. The non-elected claims 13-19 are withdrawn.
Pending elected claims 2-12 of which claims 1 and 20 are independent claims, are examined on their merits, infra.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2024-0086104 filed in Korea on July 1, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted February 28, 2025.
Drawings
The drawings filed February 28, 2025 are accepted by the examiner.
Abstract
An abstract has not been filed. The abstract should be limited to 150 words. Correction is required. See MPEP § 608.01(b).
Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. implied language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10, 12 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210202647 Al) in view of Niioka (US 20140292732 A1).
As to Claim 1:
Wang et al. discloses a display device (Wang, see Abstract, where Wang discloses that a display apparatus includes: a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT) comprising: a substrate (Wang, see substrate 110 in figure 1 and paragraph [0055], where Wang discloses pixels PX including various display devices, such as organic light-emitting devices (OLEDs), may be positioned in a first direction and a second direction in a display area DA of a substrate 110. The pixels PX may include a display device and a pixel circuit for driving the display device. Various wirings and driving circuits, i.e., a scan driver, a multiplexer (MUX), and a data driver for transmitting electrical signals to the display area DA may be positioned in a peripheral area PA of the substrate 110); a first scan line (Wang, see SLK in figure 8) and a second scan line (Wang, see SLK+1 in figure 8) disposed on the substrate (Wang, see paragraph [0055], where Wang discloses pixels PX including various display devices, such as organic light-emitting devices (OLEDs), may be positioned in a first direction and a second direction in a display area DA of a substrate 110. The pixels PX may include a display device and a pixel circuit for driving the display device. Various wirings and driving circuits, i.e., a scan driver, a multiplexer (MUX), and a data driver for transmitting electrical signals to the display area DA may be positioned in a peripheral area PA of the substrate 110); a data line (Wang, see DL1 in figure 8) intersecting the first scan line (Wang, see SLK in figure 8) and the second scan line (Wang, see SLK+1 in figure 8); a first pixel circuit portion (Wang, see PX (k,p) in figure 8) and a second pixel circuit portion adjacent to each other in a first direction (Wang, see PX (k, p+1) in figure 8) with the data line therebetween (Wang, see DL1 in figure 8); and a shielding pattern disposed between the first pixel circuit portion and the second pixel circuit portion (Wang, see paragraphs [0056] and [0008], where Wang discloses that the pixel circuit and a driving circuit may be implemented using a plurality of thin-film transistors (TFTs) and formed above the substrate 110. A first shielding layer configured to overlap the first TFT, the first shielding layer interposed between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT, the first shielding layer interposed between the substrate and the second TFT), wherein each of the first pixel circuit portion (Wang, see PX (k,p) in figure 8) and the second pixel circuit portion (Wang, see PX (k, p+1) in figure 8) comprises: a first transistor (Wang, see T1 in figure 7) including a first gate electrode (Wang, see G1 on T1 in figure 7) connected to a first node (Wang, see G1 on T1 connected to N in figure 7), and a first electrode (Wang, see E11 in T1 of figure 7) connected to a second node (Wang, see node between E11 in T1 and E52 of T5 in figure 7); and a second transistor (Wang, see T2 in figure 7) connected between the first node (Wang, see T2 connected to node N through T1 in figure 7) and the data line (Wang, see DATA line 171 connected to T2 in figure 7) and including a second gate electrode capable of receiving a first scan signal (Wang, see G2 in T2 connected to GWP in figure 7), and the shielding pattern includes a portion protruding toward the first pixel circuit portion in a plan view (Wang, see paragraphs [0056] and [0008], where Wang discloses that the pixel circuit and a driving circuit may be implemented using a plurality of thin-film transistors (TFTs) and formed above the substrate 110. A first shielding layer configured to overlap the first TFT, the first shielding layer interposed between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT, the first shielding layer interposed between the substrate and the second TFT).
Wang differs from the claimed subject matter in that Wang does not explicitly disclose asymmetrical. However in an analogous art, Niioka discloses asymmetrical (Niioka, see paragraph [0245], where Niioka discloses that the present embodiment is not limited thereto, but the position in the X-axis direction of the thin film transistor of each pixel composing the vertically adjacent pixel pair may be disposed to become asymmetrical by changing the layout structure of the light shielding section).
It would have been obvious to one of ordinary skill in the art to modify the invention of Wang with Niioka. One would be motivated to modify Wang by disclosing asymmetrical as taught by Niioka, and thereby it is desirable to set the amount of the 3D crosstalk at a predetermined level or less (Niioka, see paragraph [0024]).
As to Claim 3:
Wang in view of Niioka discloses that the display device of claim 1, wherein the shielding pattern transmits a constant voltage (Wang, see paragraph [0017], where Wang discloses that the first shielding layer may be electrically connected to a power line for applying a power voltage).
As to Claim 10:
Wang in view of Niioka discloses that the display device of claim 1, further comprising a first power line electrically connected to a second electrode of the first transistor and transmitting a first power voltage (Wang, see ELVDD to N to T1 and ELVDD to T5 to T1 in figure 7), wherein the shielding pattern is electrically connected to the first power line (Wang, see paragraph [0017], where Wang discloses that the first shielding layer may be electrically connected to a power line for applying a power voltage).
As to Claim 12:
Wang in view of Niioka discloses that the display device of claim 1, wherein the first scan line and the second scan line are repeatedly disposed for each pixel row in pairs (Wang, see PX have scan lines GWP, GWN, GI in figure 7).
As to Claim 20:
Wang et al. discloses an electronic device (Wang, see Abstract, where Wang discloses that a display apparatus includes: a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT) comprising: a display module (Wang, see DA in figure 1); and a processor electrically connected to the display module (Wang, see paragraph [0052], where Wang discloses that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor ( e.g., one or more programmed microprocessors and associated circuitry) to perform other functions), wherein the display module (Wang, see DA in figure 1) comprises: a substrate (Wang, see substrate 110 in figure 1 and paragraph [0055], where Wang discloses pixels PX including various display devices, such as organic light-emitting devices (OLEDs), may be positioned in a first direction and a second direction in a display area DA of a substrate 110. The pixels PX may include a display device and a pixel circuit for driving the display device. Various wirings and driving circuits, i.e., a scan driver, a multiplexer (MUX), and a data driver for transmitting electrical signals to the display area DA may be positioned in a peripheral area PA of the substrate 110); a first scan line (Wang, see SLK in figure 8) and a second scan line (Wang, see SLK+1 in figure 8) disposed on the substrate (Wang, see paragraph [0055], where Wang discloses pixels PX including various display devices, such as organic light-emitting devices (OLEDs), may be positioned in a first direction and a second direction in a display area DA of a substrate 110. The pixels PX may include a display device and a pixel circuit for driving the display device. Various wirings and driving circuits, i.e., a scan driver, a multiplexer (MUX), and a data driver for transmitting electrical signals to the display area DA may be positioned in a peripheral area PA of the substrate 110); a data line (Wang, see DL1 in figure 8) intersecting the first scan line (Wang, see SLK in figure 8) and the second scan line (Wang, see SLK+1 in figure 8); a first pixel circuit portion (Wang, see PX (k,p) in figure 8) and a second pixel circuit portion adjacent to each other in a first direction (Wang, see PX (k, p+1) in figure 8) with the data line therebetween (Wang, see DL1 in figure 8); and a shielding pattern disposed between the first pixel circuit portion and the second pixel circuit portion (Wang, see paragraphs [0056] and [0008], where Wang discloses that the pixel circuit and a driving circuit may be implemented using a plurality of thin-film transistors (TFTs) and formed above the substrate 110. A first shielding layer configured to overlap the first TFT, the first shielding layer interposed between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT, the first shielding layer interposed between the substrate and the second TFT), wherein each of the first pixel circuit portion (Wang, see PX (k,p) in figure 8) and the second pixel circuit portion (Wang, see PX (k, p+1) in figure 8) comprises: a first transistor (Wang, see T1 in figure 7) including a first gate electrode (Wang, see G1 on T1 in figure 7) connected to a first node (Wang, see G1 on T1 connected to N in figure 7), and a first electrode (Wang, see E11 in T1 of figure 7) connected to a second node (Wang, see node between E11 in T1 and E52 of T5 in figure 7); and a second transistor (Wang, see T2 in figure 7) connected between the first node (Wang, see T2 connected to node N through T1 in figure 7) and the data line (Wang, see DATA line 171 connected to T2 in figure 7) and including a second gate electrode capable of receiving a first scan signal (Wang, see G2 in T2 connected to GWP in figure 7), and the shielding pattern includes a portion protruding toward the first pixel circuit portion in a plan view (Wang, see paragraphs [0056] and [0008], where Wang discloses that the pixel circuit and a driving circuit may be implemented using a plurality of thin-film transistors (TFTs) and formed above the substrate 110. A first shielding layer configured to overlap the first TFT, the first shielding layer interposed between a substrate and the first TFT; and a second shielding layer configured to overlap).
Wang differs from the claimed subject matter in that Wang does not explicitly disclose asymmetrical. However in an analogous art, Niioka discloses asymmetrical (Niioka, see paragraph [0245], where Niioka discloses that the present embodiment is not limited thereto, but the position in the X-axis direction of the thin film transistor of each pixel composing the vertically adjacent pixel pair may be disposed to become asymmetrical by changing the layout structure of the light shielding section).
It would have been obvious to one of ordinary skill in the art to modify the invention of Wang with Niioka. One would be motivated to modify Wang by disclosing asymmetrical as taught by Niioka, and thereby it is desirable to set the amount of the 3D crosstalk at a predetermined level or less (Niioka, see paragraph [0024]).
Allowable Subject Matter
Claims 2, 4-9 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 2, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the shielding pattern and the asymmetrical portion are disposed on a same conductive layer”.
Referring to claim 4 and dependent claim 4, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the shielding pattern overlaps the data line in a plan view and extends in a second direction perpendicular to the first direction”.
Referring to claim 5 and dependent claims 6 and 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the first electrode includes a lower electrode overlapping the first gate electrode, and the first gate electrode and the lower electrode overlap each other to form a first capacitor”.
Referring to claim 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the asymmetrical portion is disposed in the first direction between the second gate electrode and the first electrode of the first pixel circuit portion in a plan view”.
Referring to claim 9, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the asymmetrical portion is a wing portion that protrudes toward the first pixel circuit portion”.
Referring to claim 11, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “further comprising a gate driver that transmits a first scan signal to the first scan line and a second scan signal to the second scan line, wherein the second scan signal changes from a turn-off voltage level to a turn-on voltage level while the first scan signal is at the turn-on voltage level, and changes to the turn-off voltage level after the first scan signal changes to the turn-off voltage level”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Chen (US 10332446 B2) discloses driving circuit includes a current drive unit and a reset compensation and light emitting control circuit. The current drive unit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series, wherein the first transistor and the second transistor include a silicon semiconductor layer. The reset compensation and light emitting control circuit is coupled to the current drive unit. The reset compensation and light emitting control circuit includes a third transistor connected to a control terminal of the first transistor, wherein the third transistor is an oxide semiconductor transistor.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624