Prosecution Insights
Last updated: October 01, 2026
Application No. 19/067,243

MOUNTING DEVICE

Non-Final OA §102§103§112
Filed
Feb 28, 2025
Priority
Sep 13, 2022 — JP 2022-144947 +1 more
Examiner
YAZBACK, MAHER
Art Unit
1735
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Toray Industries Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
52 granted / 68 resolved
+11.5% vs TC avg
Strong +24% interview lift
Without
With
+23.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
18 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
60.8%
+20.8% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 68 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 3 and 6 objected to because of the following informalities: Claim 3, lines 3-4 recites the limitation “irradiate light containing wavelengths that pass through the chip component toward the chip component” which is grammatically incorrect. For the purpose of this examination, the limitation will be interpreted as “irradiate light, containing wavelengths that pass through the chip component, toward the chip component”. Claims 4 and 5 are objected to due to their dependence on claim 3. Claim 6, lines 2-3 recites the limitation “irradiate light containing wavelengths that pass through the chip component toward the chip component from below the chip component” For the purpose of this examination, the limitation will be interpreted as “irradiate light, containing wavelengths that pass through the chip component, toward the chip component and from below the chip component”. Claim 7 is objected to due to its dependence on claim 6. Appropriate correction is required. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “recognition unit” in claims 1-7. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3, lines 2-4 recites the limitation “a transmission light source disposed below the chip component and configured to irradiate light, containing wavelengths that pass through the chip component, toward the chip component”; however, it is not clear if the transmission light source is the same element as the reflection light source referenced in claim 1, lines 9-10. Specifically, the limitations appear to describe using the transmission light source and/or the reflection light source to irradiate chip and substrate recognition marks and are both disclosed in the specification as being positioned below the chip (or on the side of the attachment tool) in the chip mounting system for directing light towards the substrate (see specification paragraphs [0016]; [0021]). For the purpose of this examination, the transmission light source and the reflection light source will be interpreted as the same element in the chip mounting system. Claims 4 and 5 are rejected to due to their dependence on claim 3. Claim 6, lines 2-3 recites the limitation “a transmission light source configured to irradiate light, containing wavelengths that pass through the chip component, toward the chip component and from below the chip component”; however, it is not clear if the transmission light source is the same element as the reflection light source referenced in claim 1, lines 9-10. Specifically, the limitations appear to describe using the transmission light source and/or the reflection light source to irradiate chip and substrate recognition marks and are both disclosed in the specification as being positioned below the chip (or on the side of the attachment tool) in the chip mounting system for directing light towards the substrate (see specification paragraphs [0016]; [0021]). For the purpose of this examination, the transmission light source and the reflection light source will be interpreted as the same element in the chip mounting system. Claim 7 is rejected due to its dependence on claim 6. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamauchi et al. (US 12261070 B2 – hereinafter “Yamauchi ‘070”). Regarding claim 1, Yamauchi ‘070 discloses a mounting device (1) configured to mount a chip (CP) component having a chip recognition mark (MC2a, MC2b) for alignment and a substrate (WT) having a substrate recognition mark (MC1a, MC1b) for alignment such that a surface having the chip recognition mark faces a surface having the substrate recognition mark, in a state in which the substrate recognition mark is covered by the chip component (Fig. 2, 16A-C; 17, 18A-C; Col. 16, lines 19-34), the mounting device comprising: an attachment tool (33H) configured to hold a surface of the chip component opposite to the surface having the chip recognition mark (Fig. 5A, 17; Col. 8, lines 61-64; Col. 9, lines 23-29; Col. 12, lines 30-40); a substrate stage (315) configured to hold the substrate (Fig. 2, 4; Col. 12, lines 30-40); a reflection light source (light sources are not illustrated but are disclosed as being part of imaging devices 35a, 35b) configured to irradiate light containing wavelengths that pass through the chip component from the attachment tool side toward the substrate (Fig. 4, 17; Col. 11, lines 22-58); and a recognition unit (351a, 351b in imaging devices 35a, 35b) configured to recognize reflected light of the light irradiated by the reflection light source, the recognition unit being configured to acquire an image formed by light that passes through the chip component and is reflected by the substrate, to acquire position information of the substrate recognition mark (Fig. 4, 17; Col. 11, lines 22-58; Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 5; Col. 39, lines 48-57). Regarding claim 2, Yamauchi ‘070 discloses the mounting device according to claim 1, as outlined above, and further discloses wherein the recognition unit is configured to acquire an image formed by light that is irradiated from the reflection light source, passes through the chip component and is reflected by the surface of the chip component having the chip recognition mark, to acquire position information of the chip recognition mark (Col. 11, lines 22-58; Col. 17, lines 20-53), and the position information of the substrate recognition mark and the position information of the chip recognition mark are used to align the substrate and the chip (Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 5). Regarding claim 3, Yamauchi ‘070 discloses the mounting device according to claim 1, as outlined above, and further discloses a transmission light source (35a, 35b – where for the purpose of this examination, the transmission light source is interpreted as the reflection light source – see 112(b) rejection above) disposed below the chip component and configured to irradiate light, containing wavelengths that pass through the chip component, toward the chip component (Fig. 2, 4; Col. 11, lines 22-58; Col. 17, lines 20-53), the recognition unit being configured to acquire an image formed by light that is irradiated from the transmission light source and has wavelengths that pass through the chip component, to acquire position information of the chip recognition mark (Fig. 4, 17; Col. 11, lines 22-58; Col. 17, lines 20-53), and the position information of the substrate recognition mark and the position information of the chip recognition mark being used to align the substrate and the chip (Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 5). Regarding claim 4, Yamauchi ‘070 discloses the mounting device according to claim 3, as outlined above, and further discloses wherein the recognition unit is configured to acquire the position information of the chip recognition mark (Fig. 4, 17; Col. 11, lines 22-58; Col. 16, line 41-57), after which the attachment tool is moved toward the substrate stage (Col. 16, line 58 - Col. 17, line 19), and the position information of the substrate recognition mark is acquired in a state in which the chip component is brought close to the substrate such that the substrate recognition mark is within a depth of field of the recognition unit (Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 19). Regarding claim 5, Yamauchi ‘070 discloses the mounting device according to claim 4, as outlined above, and further discloses wherein a relative position of the recognition unit with respect to the attachment tool is maintained after the position information of the chip recognition mark is acquired until the position information of the substrate recognition mark is acquired (Col. 19, lines 4-28 – where the limitation is interpreted as describing the conditions for bonding the chip when position deviations are below preset thresholds). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. (US 12261070 B2 – hereinafter “Yamauchi ‘070”) in view of Yamauchi et al. (US 2005/0104230 A1 – hereinafter “Yamauchi ‘230”). Regarding claim 6, Yamauchi ‘070 discloses the mounting device according to claim 1, and further discloses a transmission light source (35a, 35b – where for the purpose of this examination, the transmission light source is interpreted as the reflection light source – see 112(b) rejection above) configured to irradiate light, containing wavelengths that pass through the chip component, toward the chip component and from below the chip component (Fig. 2, 4; Col. 11, lines 22-58; Col. 17, lines 20-53), the recognition unit being configured to acquire position information of the chip recognition mark from an image formed by light that is irradiated from the transmission light source and has wavelengths that pass through the chip component and the attachment tool, after which the recognition unit is configured to acquire position information of the substrate recognition mark from an image formed by light that is irradiated from the reflection light source and is reflected by the substrate, and has wavelengths that pass through the chip component and the attachment tool (Fig. 4, 17; Col. 11, lines 22-58; Col. 17, lines 20-53), and relative position information is used to obtain a positional relationship between the substrate recognition mark and the chip recognition mark, to align the substrate and the chip (Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 19; Col. 19, lines 4-28). Yamauchi ‘070 does not disclose the attachment tool having a tool recognition mark, the recognition unit being configured to acquire position information of the chip recognition mark and position information of the tool recognition mark from an image formed by light that is irradiated from the transmission light source; acquire position information of the substrate recognition mark and position information of the tool recognition mark from an image formed by light that is irradiated from the reflection light source; and relative position information with the tool recognition mark is used to obtain a positional relationship between the substrate recognition mark and the chip recognition mark, to align the substrate and the chip. However, Yamauchi ‘230, in the same field of endeavor of chip mounting systems and methods, discloses a chip mounting system comprising an attachment tool (2, 26) having a tool recognition mark (12, 13); and a recognition unit (7, 20) (Fig. 1-4; Abstract; [0010], lines 1-6; [0037]-[0039]) configured to acquire position information of a chip recognition mark (alignment recognition mark) and position information of the tool recognition mark from an image formed by light that is irradiated from a light source (light sources are not illustrated but are disclosed as being part of recognition means/unit 7 and 20) (Fig. 1-4; Abstract; [0044]-[0049]; [0065]); acquire position information of a substrate recognition mark (alignment recognition mark) and position information of the tool recognition mark from an image formed by light that is irradiated from the light source (Fig. 1-4; Abstract; [0044]-[0049]; [0065]); and relative position information with the tool recognition mark is used to obtain a positional relationship between the substrate recognition mark and the chip recognition mark, to align a substrate and a chip (Abstract; [0044]-[0049]; [0065]). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yamauchi ‘070 with an attachment tool having a tool recognition mark and steps for calibrating the position of the attachment tool relative to the substrate, where the motivation would be to improve the precision of the chip bonding process (Yamauchi ‘230: [0049]; [0081]). Regarding claim 7, Yamauchi ‘070 in view of Yamauchi ‘230 discloses the mounting device according to claim 6, as outlined above, and further discloses wherein the position information of the substrate recognition mark and the position information of the tool recognition mark are acquired in a state in which the chip component is brought close to the substrate such that both the substrate recognition mark and the tool recognition mark are within a depth of field of the recognition unit (Yamauchi ‘070: Col. 14, line 62 – Col. 15, line 17; Col. 16, line 58 – Col. 17, line 19). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAHER YAZBACK whose telephone number is (703)756-1456. The examiner can normally be reached Monday - Friday 8:30 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michelle Iacoletti can be reached at (571)270-5789. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MAHER YAZBACK/Examiner, Art Unit 2877 /MICHELLE M IACOLETTI/Supervisory Patent Examiner, Art Unit 2877
Read full office action

Prosecution Timeline

Feb 28, 2025
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+23.9%)
2y 10m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 68 resolved cases by this examiner. Grant probability derived from career allowance rate.

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