DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parthatsarathy et al. (US 20200176054, hereinafter “Parthatsarathy”)
Regarding claim 1, Parthatsarathy discloses a memory device comprising:
a memory array (Fig. 1) comprising a plurality of memory cells, wherein respective pairs of the memory cells are grouped into super cells to store an odd number of data bits (paragraph [0041], lines 8-9); and
control logic (controller), operatively coupled with the memory array, to perform operations comprising:
receiving, from a requestor, a request for soft-bit read information (read request) corresponding to at least one super cell of the memory array;
performing, for each of the odd number of data bits, respective sets of strobe reads (the strobe reads are only operations that provide information about a particular bit or memory cell state) on a pair of memory cells that form the at least one super cell (paragraph [0070]);
generating the soft-bit read information corresponding to the at least one super cell based on combined cell state information obtained from the respective sets of strobe reads, the soft-bit read information to indicate a likelihood of the at least one super cell being misread (paragraph [0008]); and
providing, to the requestor, the soft-bit read information corresponding to the at least one super cell.
Regarding claims 2 and 9, Parthatsarathy (paragraph [0044]) discloses the memory device of claim 1 and the method of claim 8, wherein performing the respective sets of strobe reads on the pair of memory cells comprises:
performing a first set of strobe reads associated with a first read voltage level on a first memory cell of the pair of memory cells; and
performing a second set of strobe reads associated with the first read voltage level on a second memory cell of the pair of memory cells.
Regarding claims 3 and 10, Parthatsarathy discloses the memory device of claim 2 and the method of claim 9, wherein generating the soft-bit read information corresponding to the at least one super cell comprises:
logically combining results of the first set of strobe reads and the second set of strobe reads to determine soft-bit read information for a first data bit stored in the at least one super cell (paragraph [0041], lines 1-2).
Regarding claim 8, Parthasarathy discloses a method comprising:
receiving, from a requestor, a request for soft-bit read information (read operation) corresponding to at least one super cell of a memory array of a memory device, the memory array comprising a plurality of memory cells, wherein respective pairs of the memory cells are grouped into super cells to store an odd number of data bits (paragraph [0041], lines 8-9);
performing, for each of the odd number of data bits, respective sets of strobe reads on a pair of memory cells that form the at least one super cell (reading each state of a pair of cells);
generating the soft-bit read information corresponding to the at least one super cell based on combined cell state information obtained from the respective sets of strobe reads, the soft-bit read information to indicate a likelihood of the at least one super cell being misread (paragraph 0008]); and
providing, to the requestor, the soft-bit read information corresponding to the at least one super cell (paragraph [0104]).
Regarding claim 15, discloses a system comprising:
a memory device comprising a memory array comprising a plurality of memory cells, wherein a pair of the memory cells are grouped into a super cell to store an odd number of data bits (paragraph [0041], lines 7-9); and
a processing device, operatively coupled with the memory device, the processing device to request soft-bit read information (paragraph [0070], lines 1-2) corresponding to the super cell from the memory device (paragraph [0070], lines 6-9), wherein the soft-bit read information is based on combined cell state information obtained from respective sets of strobe reads performed on the pair of memory cells and indicates a likelihood of the super cell being misread (paragraph [0008]).
Allowable Subject Matter
Claims 4-7, 11-14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “performing a third set of strobe reads associated with a second read voltage level on the first memory cell of the pair of memory cells; and performing a fourth set of strobe reads associated with the second read voltage level on the second memory cell of the pair of memory cells.” in combination with the other limitations thereof as is recited in the claim. Claims 5-7 depend on claim 4.
Regarding claim 8, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “performing a third set of strobe reads associated with a second read voltage level on the first memory cell of the pair of memory cells; and performing a fourth set of strobe reads associated with the second read voltage level on the second memory cell of the pair of memory cells.” in combination with the other limitations thereof as is recited in the claim. Claims 9-14 depend on claim 8.
Regarding claim 16, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “an encoder configured to encode the odd number of data bits into a set of program states stored on a super cell of the memory array; and a decoder configured to decode the set of program states from the super cells into the odd number of data bits.” in combination with the other limitations thereof as is recited in the claim. Claims 17-20 depend on claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUAN HOANG/ Primary Examiner, Art Unit 2827
Prosecution Insights