Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Applicant’s Amendment filed April 14, 2026 is acknowledged.
- Claim(s) 1, 5, 9, 20 is/are amended
- Claim(s) 6 is/are canceled
- Claim(s) 1-5, 7-20 is/are pending in the application.
This action is non-FINAL
Response to Arguments
Applicant’s assertion, see Remarks, filed April 14, 2026, that Yoon and Lee are subject to an obligation of assignment to the same person thereby disqualifying these documents as eligible prior art is acknowledged. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Choi et al, U.S. Patent Publication No. 20190341439 and Oh et al, U.S. Patent Publication No. 20140084792.
The Applicant has failed to address the Examiner’s assertion of Official Notice that circuit connections that are directly contacting and/or connected via connection electrodes when elements are located in different layers was well known in the art. MPEP 2144.03 states that a general allegation that the claims define a patentable invention without any reference to the Examiner's assertion of Official Notice would be inadequate and, if the Applicant does not traverse the examiner's assertion of official notice, the Examiner should clearly indicate in the next Office action that the common knowledge or well-known in the art statement is taken to be admitted prior art because the Applicant failed to traverse the Examiner's assertion of official notice. Therefore, the subject matter that is the subject of the Examiner’s Official Notice is now considered to be admitted prior art.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
The application has claimed priority based on U.S. prior filed Application Serial No. 17/981346 (now U.S. Patent No. 12245479) filed on November 4, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 27, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Examiner respectfully withdraws the objection to claim 9. Applicant’s amendment has rendered the objection moot.
Drawings
Examiner respectfully withdraws the objection to the drawings in view of Applicant’s remarks dated April 14, 2026 on pages 8-10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 7-8, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication in view of Choi et al, U.S. Patent Publication No. 20190341439.
Consider claim 1, Lu teaches a display panel (see Lu figure 1A, element 20) comprising: a first pixel circuit (see Lu figure 4B, element R,G); and
a second pixel circuit adjacent to the first pixel circuit (see Lu figure 4B, element B),
wherein each of the first pixel circuit and the second pixel circuit comprises:
a driving transistor configured to output a driving current to a display element (see Lu figure 4B, element T1 and paragraph 0083, 0102 where first transistor T1 is used as a drive transistor);
a first transistor comprising a first semiconductor layer (see Lu paragraph 0129 where FIG. 6 schematically shows the semiconductor layer 102 and the first conductive layer 201 of transistors T1-T7 of the three sub-pixels 100 corresponding to FIG. 5A) and configured to transmit a first initialization voltage to a gate electrode of the driving transistor (see Lu figure 4B, element T7, INT2 and paragraph 0092 where first electrode of the seventh transistor T7 is connected with a second reset voltage terminal INT2 to receive the second reset voltage Vint2, and the second electrode of the seventh transistor T7 is connected with the first node N1); and
a second transistor comprising a second semiconductor layer and configured to transmit a second initialization voltage to a pixel electrode of the display element (see Lu figure 4B, element T6, INT3, INT1),
wherein the first initialization voltage provided to the first pixel circuit and the first initialization voltage provided to the second pixel circuit are the same (see Lu figure 4B, element INT2),
wherein the second initialization voltage provided to the first pixel circuit and the second initialization voltage provided to the second pixel circuit are different from each other (see Lu figure 4B, element INT3, INT1), and
wherein the first semiconductor layer comprises an oxide semiconductor (see Lu paragraph 0177 where material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.))
the second transistor of the first pixel circuit is connected to a second initialization voltage line configured to transmit the second initialization voltage (see Lu figure 4B, element T6, INT1, B), and
the second transistor of the second pixel circuit is connected to a third initialization voltage line configured to transmit the second initialization voltage (see Lu figure 4B, element T6, INT3, R, G),
Lu is silent regarding wherein the second initialization voltage line and the third initialization voltage line are in different layers from each other.
In a related field of endeavor, Choi teaches having different voltage lines in different layers with insulating layers between them so as to provide voltages to pixel circuits and reduce a width of wiring (see Choi paragraph 0100).
One of ordinary skill would have been motivated to have modified Lu with the teachings of Choi to have different voltage lines in different layers with insulating layers between them so as to provide voltages to pixel circuits and reduce a width of wiring using known techniques with predictable results.
Consider claim 3, Lu as modified by Choi teaches all the limitations of claim 1 and further teaches wherein the second semiconductor layer comprises an oxide semiconductor (see Lu paragraph 0177 where material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.)).
Consider claim 4, Lu as modified by Choi teaches all the limitations of claim 1 and further teaches wherein the display element connected to the first pixel circuit is configured to emit light of a first color and the display element connected to the second pixel circuit is configured to emit light of a second color (see Lu figure 4B, element R, G, B).
Consider claim 5, Lu as modified by Choi teaches all the limitations of claim 1 and further teaches wherein the first transistors of the first pixel circuit and the second pixel circuit are connected to a first initialization voltage line configured to transmit the first initialization voltage (see Lu figure 4B, element T7, INT2, R, G, B and paragraph 0092 where first electrode of the seventh transistor T7 is connected with a second reset voltage terminal INT2 to receive the second reset voltage Vint2, and the second electrode of the seventh transistor T7 is connected with the first node N1).
Consider claim 7, Lu as modified by Choi teaches all the limitations of claim 5.
Lu is silent regarding wherein the second initialization voltage line is connected to the second semiconductor layer of the second transistor of the first pixel circuit by directly contacting the second semiconductor layer, and the third initialization voltage line is connected to the second semiconductor layer of the second transistor of the second pixel circuit by using a connection electrode.
Applicant has admitted by failing to rebut Examiner’s Official Notice in response dated April 14, 2026, that it is well known in the art to have circuit connections that are directly contacting and/or connected via connection electrodes when elements are located in different layers. Further, arrangement of known circuit components in different layers absent any criticality (i.e., unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable layout arrangements, where the general conditions of a claim are disclosed in the prior art, involves only routine skill in the art, In re Aller, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e., unobvious and/or unexpected result(s)), the recited parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Specifically, Lu discloses the recited circuit components. Rearranging the components to have a different layout in different layers absent any criticality (i.e., unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation. One of ordinary skill would have been motivated to have made the recited connections using well-known connection options without inventive inspiration using known techniques with predictable results.
Consider claim 8, Lu as modified by Choi teaches all the limitations of claim 5 and further teaches further comprising: a first initialization voltage supply line in a peripheral area outside a display area, and configured to supply the second initialization voltage to the second initialization voltage line; and a second initialization voltage supply line in the peripheral area, and configured to supply the second initialization voltage to the third initialization voltage line (see Lu figure 1A, element 131, 130, 132 and paragraph 0106, 0135, 0150, 0154-0156, 0168).
Consider claim 10, Lu as modified by Choi teaches all the limitations of claim 1 and further teaches wherein the first pixel circuit and the second pixel circuit are line-symmetric with respect to a boundary line between the first pixel circuit and the second pixel circuit (see Lu figure 6, element 100a, 100b, 100c are symmetric with respect to each other each pixel includes same components and also symmetric with the pixels in the row below).
Consider claim 11, Lu as modified by Choi teaches all the limitations of claim 1 and further teaches wherein a gate of the first transistor is connected to a first gate line configured to transmit a first scan signal (see Lu figure 4B, element T7, Vrst2), and
a gate of the second transistor is connected to a second gate line configured to transmit a second scan signal (see Lu figure 4B, element T6, Vrst1).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication and Choi et al, U.S. Patent Publication No. 20190341439 in view of Cho et al, U.S. Patent Publication No. 20210241696.
Consider claim 2, Lu as modified by Choi teaches all the limitations of claim 1. Lu teaches material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.) (see Lu paragraph 0177). Lu is silent regarding having different semiconductor layers for selected transistors of a pixel.
In the same field of endeavor, Cho teaches a similar pixel circuit (see Cho figure 7) having different semiconductor layers for selected transistors of a pixel so as to stably drive the transistors and improve reliability (see Cho figure 7, element T4, T7 and paragraphs 0075, 0113, 0116, 0119).
One of ordinary skill would have been motivated to have further modified Lu with the teachings of Cho to have different semiconductor layers for selected transistors so as to improve reliability using known techniques with predictable results resulting in having the second semiconductor layer comprises a silicon semiconductor.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication and Choi et al, U.S. Patent Publication No. 20190341439 in view of Kim et al, U.S. Patent Publication No. 20180293944.
Consider claim 9, Lu as modified by Choi teaches all the limitations of claim 1. Lu is silent regarding wherein the second initialization voltage provided when the display pane is at a temperature higher than a reference temperature is different from the second initialization voltage provided when the display panel is at a temperature lower than the reference temperature.
In a related field of endeavor, Kim teaches that an initialization voltage may be increased in proportion to a measured temperature so as to reduce flickering (see Kim figure 7C and paragraphs 0110-0114). One of ordinary skill in the art would have been motivated to have modified Lu with the teachings of Kim to have the second initialization voltage provided when the display panel is at a temperature higher than a reference temperature is different from the second initialization voltage provided when the display panel is at a temperature lower than the reference temperature so as to reduce flickering using known techniques with predictable results.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication and Choi et al, U.S. Patent Publication No. 20190341439 in view of Nishiyama, U.S. Patent Publication No. 20210027709 and Akimoto et al, U.S. Patent Publication No. 20150301636.
Consider claim 12, Lu as modified by Choi teaches all the limitations of claim 1. Lu is silent regarding further comprising: a conductive layer between a substrate and a semiconductor layer of the driving transistor; a first insulating layer between the substrate and the conductive layer; and a second insulating layer between the conductive layer and the semiconductor layer of the driving transistor.
Nishiyama teaches having a drive transistor having a back gate that supplied with a constant potential so as to reduce an effect of characteristic variation and achieve favorable gray scale expression even at a low luminance (see Nishiyama paragraphs 0009-0010, 0040, 0043). Nishiyama is silent regarding specific structure/layer arrangement of a transistor having a back gate.
In a related field of endeavor, Akimoto teaches a conductive layer (see Akimoto figure 16B, element 920) between a substrate (see Akimoto figure 16B, element 900) and a semiconductor layer (see Akimoto figure 16B, element 940) of the transistor; a first insulating layer (see Akimoto figure 16B, element 915) between the substrate (see Akimoto figure 16B, element 900) and the conductive layer (see Akimoto figure 16B, element 920); and a second insulating layer (see Akimoto figure 16B, element 930) between the conductive layer (see Akimoto figure 16B, element 920) and the semiconductor layer (see Akimoto figure 16B, element 940) of the transistor.
One of ordinary skill would have been motivated to have modified Lu with the teachings of Nishiyama and Akimoto to have a driving transistor with a back gate as disclosed by Akimoto that supplied with a constant potential so as to reduce an effect of characteristic variation and achieve favorable gray scale expression even at a low luminance using known techniques with predictable results.
Consider claim 13, Lu as modified by Choi, Nishiyama and Akimoto teaches all the limitations of claim 12 and further teaches wherein a channel area of the semiconductor layer of the driving transistor overlaps the conductive layer (see Akimoto figure 16B, element 940, 920 and paragraph 0191 where semiconductor layer 940 functions as a channel formation region of the transistor).
Consider claim 14, Lu as modified by Choi, Nishiyama and Akimoto teaches all the limitations of claim 12 and further teaches wherein the conductive layer is configured to receive a constant voltage (see Nishiyama paragraphs 0009-0010, 0040, 0043).
Claim(s) 15, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication in view of Oh et al, U.S. Patent Publication No. 20140084792.
Consider claim 15, Lu teaches an electronic device comprising: a display panel (see Lu figure 1A, element 20) comprising a plurality of pixels (see Lu figure 1A, element 100); and
wherein the plurality of pixels comprises a first pixel (see Lu figure 4B, element R,G) and a second pixel (see Lu figure 4B, element B),
wherein each of the first pixel and the second pixel comprises a pixel circuit and a display element connected to the pixel circuit (see Lu figure 4B, elements T1-T7, OLED),
wherein the pixel circuit comprises: a first transistor comprising a first semiconductor layer (see Lu paragraph 0129 where FIG. 6 schematically shows the semiconductor layer 102 and the first conductive layer 201 of transistors T1-T7 of the three sub-pixels 100 corresponding to FIG. 5A) and configured to output a driving current to the display element (see Lu figure 4B, element T1 and paragraph 0083, 0102 where first transistor T1 is used as a drive transistor);
a second transistor comprising a second semiconductor layer (see Lu paragraph 0129 where FIG. 6 schematically shows the semiconductor layer 102 and the first conductive layer 201 of transistors T1-T7 of the three sub-pixels 100 corresponding to FIG. 5A) and configured to transmit the first initialization voltage to a gate electrode of the first transistor (see Lu figure 4B, element T7, N1); and
a third transistor comprising a third semiconductor layer (see Lu paragraph 0129 where FIG. 6 schematically shows the semiconductor layer 102 and the first conductive layer 201 of transistors T1-T7 of the three sub-pixels 100 corresponding to FIG. 5A) and configured to transmit the second initialization voltage to a pixel electrode of the display element (see Lu figure 4B, element T6, INT3, INT1),
wherein the first initialization voltage provided to the first pixel and the first initialization voltage provided to the second pixel are the same (see Lu figure 4B, element INT2, R, G, B),
wherein the second initialization voltage provided to the first pixel and the second initialization voltage provided to the second pixel are different from each other (see Lu figure 4B, element INT1, INT3, R, G, B), and
wherein the second semiconductor layer comprises an oxide semiconductor (see Lu paragraph 0177 where material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.)).
Lu is silent regarding a voltage generator configured to provide a first initialization voltage and a second initialization voltage to the plurality of pixels.
In the same field of endeavor, Oh teaches a voltage generator configured to provide a first initialization voltage and a second initialization voltage to the plurality of pixels so as to generate voltages used to drive a pixel (see Oh figure 12, element 170 and paragraph 0125).
One of ordinary skill in the art would have been motivated to have modified Lu with the teachings of Oh to have a voltage generator to provide a first initialization voltage and a second initialization voltage to the plurality of pixels so as to generate voltages used to drive a pixel using known techniques with predictable results.
Consider claim 17, Lu as modified by Oh teaches all the limitations of claim 15 and further teaches wherein the third semiconductor layer comprises an oxide semiconductor (see Lu paragraph 0177 where material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.)).
Consider claim 18, Lu as modified by Oh teaches all the limitations of claim 15 and further teaches wherein the display element of the first pixel is configured to emit light of a first color and the display element of the second pixel is configured to emit light of a second color (see Lu figure 4B, element R, G, B).
Consider claim 19, Lu as modified by Oh teaches all the limitations of claim 15 and further teaches wherein the second transistors of the first pixel and the second pixel are connected to a first initialization voltage line configured to transmit the first initialization voltage (see Lu figure 4B, element T7, INT2, R, G, B and paragraph 0092 where first electrode of the seventh transistor T7 is connected with a second reset voltage terminal INT2 to receive the second reset voltage Vint2, and the second electrode of the seventh transistor T7 is connected with the first node N1),
the third transistor of the first pixel is connected to a second initialization voltage line configured to transmit the second initialization voltage (see Lu figure 4B, element T6, INT1, B), and
the third transistor of the second pixel is connected to a third initialization voltage line configured to transmit the second initialization voltage (see Lu figure 4B, element T6, INT3, R, G).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication and Oh et al, U.S. Patent Publication No. 20140084792 in view of Cho et al, U.S. Patent Publication No. 20210241696.
Consider claim 16, Lu as modified by Oh teaches all the limitations of claim 15. Lu teaches material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.) (see Lu paragraph 0177). Lu is silent regarding having different semiconductor layers for selected transistors of a pixel.
In the same field of endeavor, Cho teaches a similar pixel circuit (see Cho figure 7) having different semiconductor layers for selected transistors of a pixel so as to stably drive the transistors and improve reliability (see Cho figure 7, element T4, T7 and paragraphs 0075, 0113, 0116, 0119).
One of ordinary skill would have been motivated to have further modified Lu with the teachings of Cho to have different semiconductor layers for selected transistors so as to improve reliability using known techniques with predictable results resulting in having the second semiconductor layer comprises a silicon semiconductor.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al, International Patent Publication No. WO 2021/223101 (publication date November 11, 2021), Examiner is using U.S. Patent Publication No. 20230133179 (National Stage Application) as English translation of International Publication and Oh et al, U.S. Patent Publication No. 20140084792 in view of Kim et al, U.S. Patent Publication No. 20180293944.
Consider claim 20, Lu as modified by Oh teaches all the limitations of claim 19. Lu is silent regarding further comprising a sensor configured to detect a temperature, wherein the voltage generator is configured to generate the second initialization voltage differently according to the temperature.
In a related field of endeavor, Kim teaches that an initialization voltage may be increased in proportion to a measured temperature so as to reduce flickering (see Kim figure 7C and paragraphs 0110-0114). One of ordinary skill in the art would have been motivated to have modified Lu with the teachings of Kim to have the voltage generator generate the second initialization voltage differently according to the temperature so as to reduce flickering using known techniques with predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Hwang, U.S. Patent Publication No. 20160125809 (thin film transistor substrate), Kim et al, U.S. Patent Publication No. 20200066212 (pixel circuit), Peng et al, U.S. Patent Publication No. 10657894 (pixel circuit), Park et al, U.S. Patent Publication No. 20220199026 (display device), Yang et al, U.S. Patent Publication No. 20210167161 (display substrate), Kim et al, U.S. Patent Publication No. 20060262130 (display), Xian et al, U.S. Patent Publication No. 20220320202 (display panel)
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/Dorothy Harris/Primary Examiner, Art Unit 2625
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