DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1 and 16.
b. Pending: 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 14, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BLOEMER PG PUB 20220246183 (hereinafter BLOEMER).
Regarding independent claim 1, Bloemer teaches a memory device (figure 2), comprising:
a plurality of command/address (CA) inputs (CA input pins 206 in figure 2, [0037], “…command address (CA) input pins 206…”);
a plurality of data inputs/outputs (DQs) (DQ/DQX/EDC 216 in figure 2, [0037], “…one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216…”); and
a fine-grained CA training mode (CATM) circuit (200 in figure 2) coupled to the CA inputs (CA input pins 206 in figure 2) and coupled to the DQs (DQ/DQX/EDC 216 in figure 2, [0037], “…one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216…”), the fine-grained CATM circuit configured to:
capture a CA sample from the CA inputs (Bloemer teaches applying a CA pattern to the CA pins and capturing/checking the received pattern, [0037], “…memory controller applies a data pattern to one or more CA input pins 206…”, [0073], “…At step 406, the memory device compares the data pattern received at each CA input pin 206 with the data pattern generated by each CA LFSR 210 for the corresponding CA input pin 206…”);
perform a plurality of operations on the CA sample (Bloemer teaches respective comparison operations performed by the XOR gates 212, [0037], “…XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210…”), wherein each operation is performed on an exclusive subset of the CA sample ([0045], “… In mode 1, the memory controller and DRAM test setup time and hold time for each command address input pin 206 independently…The circuitry for each command address input pin 206 includes a CA LFSR 210…” Under BRI, the entire captured CA pattern constitutes the CA sample, while each individual CA-input value is a subset of that sample, XOR operation #1 operates on CA[0], XOR operation #2 operates on CA[1]);
generate a plurality of output values, wherein each operation generates an output value (Bloemer XOR comparisons generate respective pass/fail values, [0037], “…XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210…”); and
drive the plurality of output values over the plurality of DQs ([0073], “…At step 408, the memory device transmits the comparison results for each CA input pin 206 to the corresponding data pins, such as DQ, DQX, and/or EDC pins 216…”)
Regarding claim 2, Bloemer teaches the memory device of claim 1, wherein the exclusive subset of the CA sample comprises at least one CA input (Under BRI, the entire captured CA pattern constitutes the CA sample, while each individual CA-input value is a subset of that sample, XOR operation #1 operates on CA[0], XOR operation #2 operates on CA[1]), and wherein at least one of the output values generated by the operation performed on the exclusive subset is driven on at most one DQ ([0037], “…XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210… XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210…” step 408 in figure 4, “TRANSMIT COMPARISON RESULTS FOR EACH CA INPUT TO CORRESPONDING DATA OUTPUT PIN, [0073], “…At step 408, the memory device transmits the comparison results for each CA input pin 206 to the corresponding data pins, such as DQ, DQX, and/or EDC pins 216…”, thus a result associated with a particular independently trained CA input is transmitted to its corresponding data output, rather than necessarily being duplicated over every DQ).
Regarding claim 14, Bloemer teaches the memory device of claim 1, wherein the memory device further comprises an IO circuit (multiplexer 202 and transmitter 214) coupled to the fine-grained CATM circuit (200 in figure 2) and coupled to the DQs (216 in figure 2).
Regarding independent claim 16, Bloemer teaches a method for fine-grained Command/Address training on a memory device coupled to a plurality of command/address (CA) inputs (CA input pins 206 in figure 2, [0037], “…command address (CA) input pins 206…”) and to a plurality of data inputs/outputs (DQs) (DQ/DQX/EDC 216 in figure 2, [0037], “…one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216…”), the method comprising:
receiving a command to enter a command/address Training Mode (CATM) (figure 4, step 402, [0071], “…a method 400 begins at step 402, where a memory device determines that the memory device has received a command address (CA) training entry command…”);
in response to receiving the command, entering the CATM (step 404 in figure 4);
receiving a sample signal (Bloemer receives a clock signal used to determine when the CA inputs are sampled, [0074], “…the DRAM may sample certain CA input pins 206 on one edge of the clock signal and other CA input pins 206 at a previous edge of the clock signal and/or a subsequent edge of the clock signal…”);
in response to receiving the sample signal, capturing a CA sample from the plurality of CA inputs ([0074], “…the DRAM may sample certain CA input pins 206 on one edge of the clock signal and other CA input pins 206 at a previous edge of the clock signal and/or a subsequent edge of the clock signal…”);
performing a plurality of operations on the CA sample, wherein each operation is performed on an exclusive subset of the CA sample (Bloemer performs an independent comparison operation for each respective CA input, [0072]-[0073], “..circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuitry for each command address input pin 206 further includes a PRBS checker, such as XOR gate 212, that compares the PRBS generated by CA LFSR 210 with a PRBS received from the memory controller via receiver 208…At step 406, the memory device compares the data pattern received at each CA input pin 206 with the data pattern generated by each CA LFSR 210 for the corresponding CA input pin 206…”);
yielding a plurality of results , wherein each operation yields a result (Bloemer teaches each respective XOR comparison produces a pass/fail output, [0073], [0077]);
transmitting the plurality of results over a plurality of DQs, wherein each result is transmitted over a different DQ (step 408/416 in figure 4, [0073], “…At step 408, the memory device transmits the comparison results for each CA input pin 206 to the corresponding data pins, such as DQ, DQX, and/or EDC pins 216 …”, [0077]); and
exiting the CATM in response to receiving a CATM exit indication (step 418/420 in figure 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over BLOEMER PG PUB 20220246183 (hereinafter BLOEMER), in view of KOSTINSKY PG PUB 20140189224 (hereinafter KOSTINSKY).
Regarding claim 3, Bloemer teaches the memory device of claim 1, wherein the memory device comprises fourteen CA inputs and four DQs, wherein an exclusive-or operation is performed on four exclusive subsets of the CA sample to generate four output values, wherein three of the four exclusive subsets comprise four CA inputs and one comprises two CA inputs, and wherein the fine- grained CATM circuit is configured to drive each of the four output values over a different DQ (Bloemer teaches the basic architecture, teaches individually processing CA information and providing resulting comparison values through corresponding data pins, thus Bloemer teaches CA information[Wingdings font/0xE0]XOR-type operation[Wingdings font/0xE0]output result[Wingdings font/0xE0]DQ output, KOSTINSKY teaches adapting CA information to available DQ resources, KOSTINSKY teaches fine-grained mapping between CA pins and DQ pins, [0085], “…eight target CA pins mapped to 16 DQ pins for each two bytes… Each CA pin is mapped to two data device pins (e.g., X1 and X2)…” Thus, KOSTINSKY established that the relationship between the number of CA signals and available DQ outputs is an implementation-dependent mapping relationship, rather than requiring a fixed one-CA-to-one-DQ architecture. Bloemer does not expressly teach 14 CA inputs groups as 4+4+4+2, KOSTINSKY does not expressly teach that numerical grouping either. Nevertheless, it would have been obvious to a person of ordinary skill in the art, when implementing Bloemer CA-training operations with only four available DQ result channels, to aggregate the CA inputs into four non-overlapping groups and perform a known XOR reduction on each group, because Bloemer already teaches XOR processing and KOSTINSKY teaches adapting the mapping of CA information to the available SQ resources. For 14 CA inputs divided among four output channels, the balanced exhaustive group as 4+4+4+2, would have been one of a finite number of predictable grouping, yielding four output values for four available DQs).
Regarding claim 4, the combination of Bloemer and KOSTINSKY teaches the memory device of claim 1, wherein the memory device comprises fourteen CA inputs and eight DQs, wherein an exclusive-or operation is performed on seven exclusive subsets of the CA sample to generate seven output values, wherein each exclusive subset comprises two CA inputs, and wherein the fine-grained CATM circuit is configured to drive each of the seven output values over a different DQ (Bloemer teaches the basic architecture, teaches individually processing CA information and providing resulting comparison values through corresponding data pins, thus Bloemer teaches CA information[Wingdings font/0xE0]XOR-type operation[Wingdings font/0xE0]output result[Wingdings font/0xE0]DQ output, KOSTINSKY teaches the flexible CA vs DQ mapping principles, given 14 CA inputs and an interface having 8 DQs, it would have been obvious to reduce pairs of CA values to respective output results using the known XOR operation, resulting in CA0/CA1[Wingdings font/0xE0]XOR[Wingdings font/0xE0]result 0, CA2/CA3[Wingdings font/0xE0]XOR[Wingdings font/0xE0]result 1, that provides seven mutually exclusive two-CA subsets, seven XOR results, and leaves one of the eight available DQs unused. The precise pairing of 14 inputs into 7 two0input subsets represents a predictable implementation of the known CA-processing and configurable CA/DQ mapping teachings of Bloemer and KOSTINSK, because every CA input is included once, the subsets do not overlap, and each XOR reduction produces one corresponding result for transmission over a respective available DQ).
Claims 5, 10-13, 15, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over BLOEMER PG PUB 20220246183 (hereinafter BLOEMER), in view of MOZAK PG PUB 20230297523 (hereinafter MOZAK).
Regarding claim 5, Bloemer teaches the memory device of claim 1, but does not teach wherein the memory device comprises fourteen CA inputs and sixteen DQs, wherein an identity operation is performed on fourteen exclusive subsets of the CA sample to generate fourteen output values, wherein the fourteen exclusive subsets comprise one CA input, and wherein the fine-grained CATM circuit is configured to drive each of the fourteen output values over a different DQ (Bloemer teaches the basic architecture, teaches individually processing CA information and providing resulting comparison values through corresponding data pins, thus Bloemer teaches CA information[Wingdings font/0xE0]XOR-type operation[Wingdings font/0xE0]output result[Wingdings font/0xE0]DQ output. Mozak teaches returning individual captured CA values themselves over respective DQ lines without XOR compression. It would have been obvious to substitute Mazak known identifying/pass-through reporting for Bloemer’s pass/fail reporting where sufficient DQ resources are available, because doing so conveys the actual sampled CA values and therefore providing the controller with more detained CA-training information. With 14 CA signals an d16 DQs, fourteen sampled values ca be transmitted over 14 respectively DQ channels while two remain unused).
Regarding claim 10, the combination of Bloemer and Mozak teaches the memory device of claim 1, wherein at least one exclusive subset of the CA sample comprises at most one CA input, and wherein the operation performed on the at least one exclusive subset is an identity function (Bloemer teaches individually processing each CA input, Mozak teaches an LPDDR_CBT implementation in which the captured CA values themselves are returned over the data bus. Mozak teaches sampling CA[6:0] and returning the sampled CA pattern over DQ [6:0]. Thus Mozak operation is an identify/pass-through function. It would have been obvious to use Mozak known identity reporting in Bloemer individual-CA training architecture where the actual sampled CA value, rather than merely a pass/fail indication, is desired by the controller).
Regarding claim 11, the combination of Bloemer and Mozak teaches the memory device of claim 1, wherein at least one exclusive subset of the CA sample comprises more than one CA input, and wherein the operation performed on the at least one exclusive subset is an exclusive-or function (Bloemer teaches the exclusive-subset/per-CA training architecture. Mozak teaches XOR circuitry 383 for processing sampled CA information and generating a parity/compressed value. Mozak explains that the sampled CA pattern may be compressed using XOR circuitry before the result is retuned over the data bus. It would have been obvious to use Mozak known XOR reduction on a selected group of Bloemer CA values to reduce multiple CA values to a single training result for transmission through an available DQ).
Regarding claim 12, the combination of Bloemer and Mozak teaches the memory device of claim 1, wherein the memory device further comprises a command decoder that is coupled to the CA inputs and coupled to the fine-grained CATM circuit, wherein the command decoder is configured to detect a command/address Training Mode (CATM) enter command on the CA inputs, and wherein the fine-grained CATM circuit is further configured to detect the CATM enter command from the command decoder (Bloemer teaches entering and operating in A CA- interface training mode. Mozak teaches a memory device entering command-bus/CATM training responsive to a received command, including the command-processing circuitry necessary to recognize the training command. It would have been obvious to employ Mozak command-decoder-controlled training entry in Bloemer because decoding a controller-issued training command provides a conventional mechanism for coordinating ebtry into CA training).
Regarding claim 13, the combination of Bloemer and Mozak teaches the memory device of claim 12, wherein the CATM enter command comprises a multi-purpose command (MPC) with an op-code of 0000 0011 b (Mozak teaches use of an MPC (multi-purpose command) in connection with DDR5 CATM, [0072], “…logic and/or features of memory controller 220 may enable CATM by issuing a multipurpose command (MPC)…”, Mozak further teaches that the CATM enter command may be triggered by programming a specific bit pattern into the multipurpose register. Mozak does not expressly teach the particular opcode assigned to the CATM-enter MPC is 0000 0011 b. However, once an MPC is used to uniquely identify the CATM-enter operation, the particular binary value assigned to that known command merely identifies the command to the command-decoding circuitry. Selecting 0000 0011 b from the finite set of available binary command encoding would have been an obvious implementation choice yielding predictable result of uniquely identifying and decoding the CATM-enter MPC).
Regarding claim 15, the combination of Bloemer and Mozak teaches the memory device of claim 1, wherein the memory device is configured for on-die termination (ODT) (Mozak teaches in figure 1 on-die terminator 146).
Claim 19 is rejected for the same reasons set forth above with respect to claim 10.
Claim 20 is rejected for the same reasons set forth above with respect to claim 11.
Claims 6, 18 are rejected under 35 U.S.C. 103 as being unpatentable over BLOEMER PG PUB 20220246183 (hereinafter BLOEMER), in view of Gans PG PUB 20200004420 (hereinafter Gans).
Regarding claim 6, Bloemer teaches the memory device of claim 1, wherein the memory device further comprises a plurality of banks (it is known in the field that device conventionally contains a plurality of Bank for the purpose of improving performance, such as enabling bank interleaving/parallelism), but does not teach wherein the fine-grained CATM circuit is further configured to: determine a configuration of the plurality of banks, wherein the exclusive subset of the CA sample on which each operation is performed is based on the determined configuration.
Gans teaches in [0039] that “the semiconductor device includes a memory array including a plurality of physical memory banks 310(0)-310(15) and 320(0)-320(15)”. Gans teaches in [0028] that mode register 225 stores bank-architecture information, including selectable bank architecture ([0105], “…circuits of a semiconductor device may provide internal signals and decoded addresses based on the bank architecture set, for example, by information stored in a mode register...”)
Bloemer already teaches performing the CATM processing on selected/subdivided portions of the received CA information, Gans supplies the additional teaching that which CA/address bits have bank significance changes according to the selected bank architecture. Therefore, the bank configuration determines which CA/address bits constitute the bank related subset and how those bits are interpreted. Applying this teaching to Bloemer’s fine grained CATM would cause Bloemer subset processing to be performed according to the CA-bit organization for the detected /configured bank architecture. It would have been obvious to configure Bloemer fine grained CATM circuitry ti determine the bank architecture and select/process the corresponding CA/address subsets as taught by Gans, because Gans teaches that different selectable bank architectures require different decoding and mapping of the address bits to the memory banks. Such modification would permit Bloemer CA training circuitry to correctly train CA information for memory device operating under different supported bank configurations.
Claim 18 is rejected for the same reasons set forth above with respect to claim 6.
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over BLOEMER PG PUB 20220246183 (hereinafter BLOEMER), in view of Morris PG PUB 20180181504 (hereinafter Morris).
Regarding claim 7, Bloemer teaches the memory device of claim 1, but does not teach wherein the memory device further comprises a clock input with a rising edge and a chip select input, wherein the chip select input is aligned to the clock input, and wherein the fine-grained CATM circuit is further configured to capture the CA sample based on the chip select input and the clock input.
However, Morris teaches a chip-select signal BCS_n and clock signals BCK_t/BCK_c and teaches their timing relationship ([0030], “…BCS_n should ideally be synchronous with clock signal BCK_t, BCK_c…”). Morris further teaches in abstract to “adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal” an din [0041] “ adjust a relative timing between the chip select signal BCS_n and the clock signal BCK_t, BCK_c based on samples of the chip select signal BCS_n sampled with the clock signal”.
It would have been obvious to employ Morris chip select/clock alignment in Bloemer’s CA training architecture to improve reliable timing and capture of CA information.
Regarding claim 8, the combination of Bloemer and Morris teaches the memory device of claim 7, wherein the fine-grained CATM circuit is further configured to capture the CA sample when the chip select input is asserted low on a rising edge of the clock input (figures 5, 7, [0103], “…for each relative delay, sample the predetermined chip select signal at the one or more data buffers at rising … edges of the clock signal.”)
Claims 9, 17 are rejected under 35 U.S.C. 103 as being unpatentable over BLOEMER PG PUB 20220246183 (hereinafter BLOEMER), in view of Morris PG PUB 20180181504 (hereinafter Morris), further in view of MOZAK PG PUB 20230297523 (hereinafter MOZAK).
Regarding claim 9, the combination of Bloemer and Morris teaches the memory device of claim 7, but does not teach wherein the chip select input is a first chip select input, and wherein the fine-grained CATM circuit is further configured to: receive a second chip select input; and based on the second chip select input, hold the CA sample for a maximum of four clock cycles, wherein the second chip select input is asserted high.
Mozak teaches in figure 8 command-bus training in which captured CA information is maintained/evaluated during a multi-cycle training interval and subsequently returned through the data interface. The claimed maximum of 4 clock cycles represents selection of the duration for which the captured sample is retained during the training interval.
Regarding claim 17, claim 17 is rejected for the same reason set forth above with respect to claims 8 and 9.
Bloemer teaches the underlying CA-training method of claim 16. Morris teaches sampling/alignment of an active low chip select signal relative to rising clock edge, as discussed for claim 8. The additional second chip select /high/four cycle holding feature is rejected for the same reason discussed with respect to claim 9.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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