Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 4, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 6-7 and 9-10 are objected to because of the following informalities:
Claim 6 – the brackets encompassing the abbreviation for voltage appear to show the text is being deleted. A suggestion would be to remove the brackets and show the value, for example, as either -2V or -2 V.
Claim 7 (line 1) – the comma is missing at the end of the preamble.
Claim 7 (lines 8-10) – recites "wherein the third capacitance element includes: a third terminal connected to the second terminal; and a fourth terminal connected to the driving buffer circuit". It is unclear where the first and second terminal are located for the third capacitance. A suggestion to rewrite this could be, "wherein the third capacitance element includes: a first terminal connected to the second terminal of the first capacitance; and a second terminal connected to the driving buffer circuit".
Claim 9 (line 2) – recites "a voltage generation circuit according to Claim 1". As this claim depends on claim 1, it appears this should be written as, "the voltage generation circuit according to Claim 1".
Claim 10 (lines 3-4) – recites "only a transistor configured to drive the image sensor". As this claim depends on claim 1, it appears this should be written as, "only the transistor configured to drive the image sensor".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 7 (lines 3-4) recites "as the transistor, a first transistor and a second transistor". It is unclear how the transistor can encompass a plurality of transistors. The transistor was defined in claim 1 wherein a power source (VDD) or ground voltage (VSS) is input to the transistor. As shown in Figs. 2/5, VDD/VSS is input into SW11; Figs. 9/10, VDD/VSS is input into SW31; and Fig. 12, VSS is input into SW41. The figures do not show SW11/SW31/SW41 changing into two transistors with an input of a power source or ground voltage.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6, 8-9 and 13-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 8 of U.S. Patent No. 12273105 B2 in view of Kimoto (US 8128556 B2, as cited by applicant); hereinafter Kimoto. Although the claims at issue are not identical, they are not patentably distinct from each other because of the anticipating limitations in bold, as shown in Table 1 below.
A summary of the pending claims of the Instant Application that are anticipated by the U.S. Patent are shown below:
Pending claims 1, 13, 14, 2, 4 are anticipated by U.S. Patent’s claim 1, 3.
Pending claim 3 is anticipated by U.S. Patent’s claim 2.
Pending claim 6 is anticipated by U.S. Patent’s claim 8.
Pending claim 8 is anticipated by U.S. Patent’s claim 4.
Pending claim 9 is anticipated by U.S. Patent’s claim 5.
Pending claim 15 is anticipated by U.S. Patent’s claim 6.
Instant Application 19/069,391
U.S. Patent No. 12273105 B2
(Pat’105)
From Claim 1:
A voltage generation circuit, comprising:
a booster circuit including a first capacitance element and a transistor;
a control buffer circuit configured to control the transistor;
a driving buffer circuit configured to drive the first capacitance element; and
a second capacitance element,
wherein a power source voltage or a ground voltage is input to the transistor, (continued to Claim 1 below).
From Claim 13:
The voltage generation circuit according to Claim 1,
wherein the power source voltage is a positive voltage.
From Claim 14:
The voltage generation circuit according to Claim 1,
wherein the ground voltage is a lower voltage than the power source voltage.
Continued from Claim 1 above:
wherein the booster circuit is configured to generate a higher first voltage than the power source voltage or generate a lower second voltage than the ground voltage when the driving buffer circuit drives the first capacitance element, and
wherein the second capacitance element is configured to hold and output the first voltage or the second voltage generated by the booster circuit.
From Claim 2:
The voltage generation circuit according to Claim 1,
wherein the control buffer circuit is configured to control the transistor by using a third voltage that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage, and
wherein the control buffer circuit is configured to control the transistor by using a fourth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage.
From Claim 4:
The voltage generation circuit according to Claim 2,
wherein the control buffer circuit includes a bootstrap circuit,
wherein the control buffer circuit is configured to generate a higher voltage than the third voltage and output the generated voltage to the transistor in a case in which the booster circuit generates the first voltage, and
wherein the control buffer circuit is configured to generate a lower voltage than the fourth voltage and output the generated voltage to the transistor in a case in which the booster circuit generates the second voltage.
From Claim 1:
A voltage generation circuit, comprising:
a booster circuit including a capacitance element and a transistor;
a control buffer circuit configured to control the transistor; and
a driving buffer circuit configured to drive the capacitance element,
wherein a power source voltage or a ground voltage is input to the transistor,
wherein the power source voltage is a positive voltage,
wherein the ground voltage is a lower voltage than the power source voltage,
wherein the booster circuit is configured to generate a higher first voltage than the power source voltage or generate a lower second voltage than the ground voltage when the driving buffer circuit drives the capacitance element, (continued to Claim 1 below).
From Claim 3:
The voltage generation circuit according to claim 1,
wherein the capacitance element is configured to hold the first voltage or the second voltage.
Continued from Claim 1 above:
wherein the control buffer circuit is configured to control the transistor by using a third voltage that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage,
wherein the control buffer circuit is configured to control the transistor by using a fourth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage,
wherein the control buffer circuit includes a bootstrap circuit,
wherein the control buffer circuit is configured to generate a higher voltage than the third voltage and output the generated voltage to the transistor in a case in which the booster circuit generates the first voltage, and
wherein the control buffer circuit is configured to generate a lower voltage than the fourth voltage and output the generated voltage to the transistor in a case in which the booster circuit generates the second voltage.
From Claim 3:
The voltage generation circuit according to Claim 1,
wherein the driving buffer circuit is configured to drive the first capacitance element by using a fifth voltage that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage, and
wherein the driving buffer circuit is configured to drive the first capacitance element by using a sixth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage.
From Claim 2:
The voltage generation circuit according to claim 1,
wherein the driving buffer circuit is configured to drive the capacitance element by using a fifth voltage that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage, and
wherein the driving buffer circuit is configured to drive the capacitance element by using a sixth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage.
From Claim 6:
The voltage generation circuit according to Claim 5,
wherein a threshold value of the strong-enhancement-type transistor is greater than or equal to -2 [V] and less than or equal to -1 [V] in a case in which the booster circuit generates the first voltage, and
wherein a threshold value of the strong-enhancement-type transistor is greater than or equal to 1[V] and less than or equal to 2 [V] in a case in which the booster circuit generates the second voltage.
From Claim 8:
The voltage generation circuit according to claim 7,
wherein a threshold value of the strong-enhancement-type transistor is greater than or equal to −2 [V] and less than or equal to −1 [V] in a case in which the booster circuit generates the first voltage, and
wherein a threshold value of the strong-enhancement-type transistor is greater than or equal to 1 [V] and less than or equal to 2 [V] in a case in which the booster circuit generates the second voltage.
From Claim 8:
The voltage generation circuit according to Claim 1,
wherein the booster circuit is a charge-pump-type booster circuit including one or more pumping packets, and
wherein each of the pumping packets includes the first capacitance element and the transistor.
From Claim 4:
The voltage generation circuit according to claim 1,
wherein the booster circuit is a charge-pump-type booster circuit including one or more pumping packets, and
wherein each of the pumping packets includes the capacitance element and the transistor.
From Claim 9:
An image sensor, comprising:
a voltage generation circuit according to Claim 1; and
two or more pixels to which the first voltage or the second voltage is input.
From Claim 5:
An image sensor, comprising:
a voltage generation circuit according to claim 1; and
two or more pixels to which the first voltage or the second voltage is input.
From Claim 15:
A scope to be inserted into a living body, the scope including the image sensor according to Claim 9,
wherein the image sensor is disposed in a distal end of the scope.
From Claim 6:
A scope to be inserted into a living body, the scope including the image sensor according to claim 5,
wherein the image sensor is disposed in a distal end of the scope.
Table 1
Pat’105 fails to disclose a second capacitance element.
However, Kimoto [Fig. 9] discloses a first capacitance element [321b] and a second capacitance element [321a]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Kimoto in the invention of Pat’105, with the expected benefit of providing a secondary battery. This method of improving Pat’105 using Kimoto was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Kimoto. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pat’105 and Kimoto to obtain the invention: incorporating the second capacitance element.
Pat’105 (claim 3) fails to disclose the capacitance elements are configured to hold and output the first voltage or the second voltage generated by the booster circuit.
However, Kimoto (specification) discloses the capacitive elements are configured to hold the voltage generated by the booster circuit and outputs the output voltage [column 10, lines 4-14]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Kimoto in the invention of Pat’105, with the expected benefit of understanding the capacitor charges. This method of improving Pat’105 using Kimoto was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Kimoto. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pat’105 and Kimoto to obtain the invention: incorporating the second capacitance element.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-9, and 13-16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kimoto (US 8128556 B2); hereinafter Kimoto.
Regarding Claim 1, Kimoto discloses a voltage generation circuit [Fig. 9], comprising: a booster circuit [321] including a first capacitance element [321b] and a transistor [322a]; a control buffer circuit [11a] configured to control the transistor; a driving buffer circuit [322b/322c] configured to drive the first capacitance element; and a second capacitance element [321a], wherein a power source voltage [VCC] or a ground voltage [GND] is input to the transistor, wherein the booster circuit is configured to generate a higher first voltage [boosted voltage to 16] than the power source voltage or generate a lower second voltage than the ground voltage when the driving buffer circuit drives the first capacitance element, and wherein the second capacitance element is configured to hold and output the first voltage or the second voltage generated by the booster circuit [column 10, lines 4-14].
Regarding Claim 8, Kimoto discloses the voltage generation circuit according to Claim 1, wherein the booster circuit is a charge-pump-type booster circuit [column 7, line 8] including one or more pumping packets [322a/321b], and wherein each of the pumping packets includes the first capacitance element and the transistor.
Regarding Claim 9, Kimoto discloses an image sensor [Fig. 1/2/3], comprising: a voltage generation circuit [see claim 1 rejection] according to Claim 1; and two or more pixels to which the first voltage or the second voltage is input [the circuit is taught in the context of the image sensor with pixels].
Regarding Claim 13, Kimoto discloses the voltage generation circuit according to Claim 1, wherein the power source voltage is a positive voltage [VCC].
Regarding Claim 14, Kimoto discloses the voltage generation circuit according to Claim 1, wherein the ground voltage is a lower voltage [ground voltage being zero volts is lower than VCC] than the power source voltage.
Regarding Claim 15, Kimoto discloses a scope to be inserted into a living body [Fig. 1/2/3], the scope including the image sensor according to Claim 9 [see claim 9 rejection], wherein the image sensor is disposed in a distal end of the scope [the image sensor is shown to be inserted into a living body].
Regarding Claim 16, Kimoto discloses a voltage generation method [Fig. 9] using a booster circuit [321] including a first capacitance element [321b] and a transistor [322a], a control buffer circuit [11a], a driving buffer circuit [322b/322c] configured to drive the first capacitance element, and a second capacitance element [321a], the method comprising: a first step [column 10, lines 8-10] in which the control buffer circuit controls the transistor; a second step in which the booster circuit generates a different first voltage [boosted voltage to 16] from a power source voltage input [output of SW18 from input VCC] to the transistor or generates a lower second voltage than a ground voltage input [GND voltage] to the transistor when the driving buffer circuit drives the first capacitance element; and a third step in which the second capacitance element holds and outputs the first voltage or the second voltage generated by the booster circuit [column 10, lines 4-14].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kimoto, in view of Maki et al. (JP 3596130 B2); hereinafter Kimoto, in view of Maki.
Regarding Claim 5, Kimoto does not explicitly disclose the voltage generation circuit according to Claim 1, wherein the transistor is configured as a strong-enhancement-type transistor.
However, Maki discloses wherein the transistor [M17] is configured as a strong-enhancement-type transistor [paragraph 0034]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Maki in the invention of Kimoto, with the expected benefit of configuring the circuit to improve efficiency. This method of improving Kimoto using Maki was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Maki. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimoto and Maki to obtain the invention: incorporating the strong-enhancement-type transistor.
Allowable Subject Matter
Claims 2-4, 6, and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following are statements of reasons for the indication of allowable subject matter:
Regarding Claim 2, Kimoto discloses wherein the control buffer circuit is configured to control the transistor by using a third voltage that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage [the output from 11a is based on VCC, which is seen as a lower voltage (a third voltage) than the boosted voltage (the first voltage), which is boosted from the VCC]. The prior art of record does not disclose nor render obvious wherein the control buffer circuit is configured to control the transistor by using a fourth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage, as cited with the rest of the claimed limitation. Dependent claim is allowed.
Regarding Claim 3, Kimoto discloses wherein the driving buffer circuit is configured to drive the first capacitance element by using a fifth voltage [via 322b] that is lower than the first voltage and is higher than the ground voltage in a case in which the booster circuit generates the first voltage [the fifth voltage is based on VCC, which is lower than the first voltage (boosted voltage)]. The prior art of record does not disclose nor render obvious wherein the driving buffer circuit is configured to drive the first capacitance element by using a sixth voltage that is higher than the second voltage and is lower than or equal to the ground voltage in a case in which the booster circuit generates the second voltage, as cited with the rest of the claimed limitation.
Regarding Claim 6, the prior art of record does not disclose nor render obvious wherein a threshold value of the strong-enhancement-type transistor is greater than or equal to -2 [V] and less than or equal to -1 [V], as cited with the rest of the claimed limitation.
Regarding Claim 10, the prior art of record does not disclose nor render obvious wherein the second capacitance element is configured to output the first voltage or the second voltage held by the second capacitance element to only a transistor configured to drive the image sensor, as cited with the rest of the claimed limitation. Dependent claims are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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