DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 03/04/2025. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (US 2021/0141692 A1, hereinafter “Agarwal”) in view of Otsuka (US 7,827,463 B2, hereinafter “Otsuka”).
Claim 1: Agarwal teaches a memory system comprising:
a plurality of first memory devices and a second memory device (e.g., Agarwal teaches a memory subsystem including multiple memory resources connected in parallel, a memory controller 130, and ECC circuitry 132 -Abstract; Fig. 1); and
a memory controller configured to control the plurality of first memory devices and the second memory device (e.g., Agarwal teaches a memory subsystem including memory controller 130 and multiple memory resources connected in parallel, including first memory resource 152 and second memory resource 154. See Abstract; Fig. 1. Agarwal further teaches a DIMM including multiple DRAM devices (DATA DRAM0–DATA DRAM8), an ECC DRAM, and a metadata DRAM under control of controller 440. See Figs. 2–4),
wherein each of the plurality of first memory devices is configured to store a first data set comprising a first set of data bits in different bit positions, each of the bit positions corresponding to a burst order and a DQ (e.g., Agarwal teaches data bits distributed across multiple DRAM devices and DQ interfaces. Figure 4 shows DATA DRAM0–DATA DRAM8 storing data bits 422 and 432 and illustrates DQ0–DQ3 interfaces for the respective DRAM devices. Figure 3 further illustrates data bits D0–D63 distributed across multiple devices and burst positions. See Figs. 3–4),
wherein the second memory device is configured to store a second data set comprising parity bits for a plurality of first data sets, respectively stored in the plurality of first memory devices (e.g., Agarwal teaches storing ECC bits separately from data bits. Figure 4 illustrates ECC bits 424 and 434 stored in ECC DRAM while corresponding data bits 422 and 432 are stored in DATA DRAM devices. Figure 2 similarly illustrates portions containing DATA and ECC fields distributed among different devices. See Figs. 2–4. Agarwal further teaches splitting a portion of data into sub-portions and generating ECC protection for the sub-portions. The Abstract states that a portion of data can include N ECC bits and that sub-portions can each include ECC bits for error correction).
However, Agarwal does not expressly disclose: “wherein a second set of data bits corresponding to a first parity bit of the parity bits are included in the plurality of first data sets, respectively, and at least two data bits of the second set of data bits have different bit positions.” However, Otsuka discloses parity generation circuit 18 that generates parity bits P(1:7) from data values C(1), C(2), C(3), and C(4). See Fig. 1. Otsuka further discloses burst write operations involving data words W1(1), W1(2), W1(3), and W1(4), wherein parity bits P0, P1, P12, P123, and P1234 are generated from data occurring at different positions in the burst sequence. See Fig. 3.
As shown in Figure 3, parity bit P1234 is generated from multiple data values C(1)-C(4), which correspond to data words W1(1)-W1(4) occurring at different burst positions. Thus, Otsuka teaches that a parity bit corresponds to multiple data bits located at different bit positions within the burst transfer operation. See Fig. 3.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize Otsuka’s parity generation arrangement in the distributed ECC architecture of Agarwal because Agarwal already distributes ECC information across multiple memory devices while Otsuka teaches generating parity bits from data bits occupying different burst positions. Combining the references would have predictably improved fault isolation and ECC coverage by ensuring that data bits participating in a parity calculation are distributed among different bit positions while maintaining Agarwal’s distributed ECC storage scheme. The combination merely applies a known parity-generation technique to a known distributed-ECC memory architecture to obtain the predictable result of enhanced error detection and correction robustness.
As per claims 14 and 19, the claimed features are rejected similarly to claim 1 above.
Claim 2: Agarwal and Otsuka teach the memory system of claim 1, wherein the first parity bit has a value based on an exclusive OR (XOR) operation performed on the second set of data bits (e.g., see Otsuka Figs. 12A-12G, 14A-14E; Agarwal check bit generation 602).
Claim 3: Agarwal and Otsuka teach the memory system of claim 1, wherein the at least two data bits have different burst orders or different DQs within corresponding at least two first data sets (e.g., Agarwal Fig. 3; BL16, DQ[0:3]).
As per claim 15, the claimed features are rejected similarly to claim 3 above.
Claim 4: Agarwal and Otsuka teach the memory system of claim 1, but fail to teach that each of the plurality of first memory devices and the second memory device is further configured to perform a first error correction operation on a data sets input or output through a corresponding memory device using a parity check matrix, and generate a first flag regarding a result of the first error correction operation, and wherein the memory controller is further configured to perform a parity check on the plurality of first data sets and the second data set received from the plurality of first memory devices and the second memory device, and obtain the first flag from the plurality of first memory devices and the second memory device to obtain first flags based on candidate error bit positions for each of the plurality of first data sets and the second data set being identified through the parity check. However, Agarwal teaches memory devices including ECC/error-control circuitry and memory controller logic for handling ECC information. Otsuka teaches syndrome generation, parity check logic, decoding of syndrome information, and error correction based on parity information. Therefore, it would have been obvious to implement the error checking and correction of Agarwal using known syndrome/parity-check techniques as taught by Otsuka to identify candidate error bit positions and indicate error correction results.
Claim 5: Agarwal and Otsuka teach the memory system of claim 4, but fail to teach the memory controller is further configured to transmit the plurality of first data sets to a host based on the candidate error bit positions not being identified through the parity check. However, Agarwal teaches transmitting data from the memory subsystem to a host after ECC processing. Otsuka teaches outputting read data when no correction is required or after error correction. Therefore, it would have been obvious to transmit the data to the host when no candidate error position is identified.
Claim 7. Agarwal and Otsuka teach the memory system of claim 4, wherein each of the plurality of first memory devices and the second memory device is further configured to provide the first flag to the memory controller through a pin assigned to the first flag or by using an extended burst length. However, Agarwal teaches providing ECC/error-related information from memory resources to the controller. It would have been obvious to output such flag information through a dedicated signal pin or through an extended burst transfer because both are predictable and conventional ways to communicate additional status information from a memory device to a controller.
Claim 16: Agarwal and Otsuka teach the memory module of claim 14, but fail to teach that each of the plurality of first memory devices and the second memory device comprise a bank array comprising a plurality of memory cells, and an on-die error correction code (ECC) circuit,5 wherein the bank array of each of the plurality of first memory devices and the second memory device comprises a normal region, in which a data set is stored, and a parity region, in which second parity bits for the data set stored in the normal region are stored, and wherein the on-die ECC circuit of each of the plurality of first memory devices and the second memory device is further configured to perform an error correction operation on a data set input or output through a corresponding memory device based on a codeword comprising the second parity bits and a parity check matrix, and generate a first flag regarding a result of the error correction operation. However, Agarwal teaches memory devices having ECC/error-control circuitry and memory arrays. And Otsuka teaches ECC circuitry, parity generation, syndrome generation, and error correction using parity check logic. Therefore, it would have been obvious to implement the memory devices of Agarwal with on-die ECC circuitry and parity storage regions using Otsuka’s known ECC architecture to provide local error correction within each memory device.
Claim 17: Agarwal and Otsuka teach the memory module of claim 16, but fail to teach that each of the plurality of first memory devices and the second memory device comprises mode register configured to store a setting value indicating either a first mode or a second mode, and wherein each of the plurality of first memory devices and the second memory device is further configured to provide only a corresponding data set based on a normal read command while the setting value indicates the first mode, and provide both the first flag regarding the result of the error correction operation and the corresponding data set based on the normal read command while the setting value indicates the second mode. However, Agarwal teaches memory device control settings and ECC-related operating modes. It would have been obvious to use a mode register to select whether only data or both data and ECC-result information are output, because mode registers are conventional in memory devices for selecting operating modes.
Claim 18: Agarwal and Otsuka teach the memory module of claim 16, but fail to teach that each of the plurality of first memory devices and the second memory device is further configured to provide the first flag regarding the result of the error correction operation to an external entity through a pin assigned to the first flag or by using an extended burst length. However, Agarwal teaches communication of ECC/error-related information from memory resources to external control logic. Therefore, it would have been obvious to communicate such flag information through a dedicated pin or an extended burst transfer as predictable ways to provide additional status information.
Claim 20: Agarwal and Otsuka teach the method of claim 19, but fail to teach: receiving the plurality of first data sets and the second data set from the plurality of first memory devices and the second memory device; performing a parity check on the plurality of first data sets and the second data set to identify candidate error bit positions for each of the plurality of first data sets and the second data set; obtaining first flags regarding results of error correction operations, performed on each of the plurality of first data sets and the second data set, by receiving a first flag from each of the plurality of first memory devices and the second memory device; and identifying a data set comprising error bits, among the plurality of first data sets and the second data set, based on the first flags. However, Agarwal teaches ECC/error-control processing in a distributed memory subsystem. Otsuka teaches receiving read data and parity bits, generating syndrome information, decoding the syndrome to identify error positions, and correcting errors. Therefore, it would have been obvious to combine Agarwal’s distributed ECC memory architecture with Otsuka’s syndrome/parity-check correction technique to identify candidate error bit positions and determine which data set contains error bits based on error result information.
Allowable Subject Matter
Claims 6, 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/21/2026
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