DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment filed 8/25/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2019/0129862 A1, hereinafter Yoshida) in view of Wei et al (US 8,949,568 B2) and Post et al. (US 2012/0311298 A1, hereinafter Post).
Regarding claim 1, Yoshida discloses a method comprising: receiving, from a host device, a memory command for a memory device ([0118], the read request, the write request, and the like from the host), the memory command comprising a logical address of the memory device and a zone identifier ([0118]-[0119], if the controller (4) receives read request including ID#0 designating the region #0 from the host 2, the controller (4) executes the data read from the region #0 by using the LBA API such that the request comprising a logical address of the memory device and a zone identifier); determining a logical zone start address using the zone identifier for a first zone of the plurality of zones ([0123], if the received read request includes ID#0, the controller (4) selects LBA API which is the API corresponding to the region); determining a zone offset as a difference of the logical address and the logical zone start address ([0155], the read operation control unit 22 reads the data from the NAND flash memory 5, based on the block number and the in-block offset); retrieving a bitmap using the zone identifier ([0170], the read operation control unit 22 refers to in-block LUT 32 corresponding to the block having the block number designated by this read request, by using this logical address); determining a physical address using the bitmap and the zone offset ([0170], the read operation control unit 22 can thereby acquire the in-block physical address (in-block offset) of the block in which the data corresponding to the logical address is stored); and executing the memory command on the memory device using the physical address ([0170], the read operation control unit 22 reads the data corresponding to the logical address from the NAND flash memory 5, based on the block number designated by the read command and the acquired in-block physical address). Yoshida differs from the claimed invention in not specifically teaching wherein the logical address targets a superblock of the memory device including a plurality of memory portions assigned to a plurality of zones, wherein each of the plurality of memory portions is assigned to a respective zone of the plurality of zones. However, Wei teaches a zone-based block management and mapping method comprising memory divisible into multiple zones, each zone comprising a plurality of physical blocks of the memory and for associating with a zone-based address map for mapping between logical and physical addresses of said zone such that the required data are directly accessible using the zone number, physical block number and block offset (col. 7 line 55 through col. 8 lines 38) in order to reduce the sizes of mapping table. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in having that the logical address targets a superblock of the memory device including a plurality of memory portions assigned to a plurality of zones, wherein each of the plurality of memory portions is assigned to a respective zone of the plurality of zones, as per teaching of Wei, in order to reduce the sizes of mapping table. The combination of Yoshida and Wei differs from the claimed invention in not specifically teaching that the bitmap identifies memory portions of the plurality of memory portions assigned to the first zone. However, Post teaches that the file system can maintain a LBA allocation table that includes a bitmap indicating which LBAs are currently allocated such that the file system can access the bitmap of LBAs associated with the NVM ([0046]-[0048]) in order to optimize operating efficiency ([0004]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshida and Wei in having that the bitmap identifies memory portions of the plurality of memory portions assigned to the first zone, as per teaching of Post, in order to optimize operating efficiency.
Regarding claim 2, Yoshida discloses that the bitmap includes a plurality of submaps of equal sizes (figure 2, regions #0 to #6), the method further comprising: retrieving a submap of the plurality of submaps for the bitmap using the zone offset, wherein determining the physical address uses the submap and the zone offset ([0263], the controller manages a flag (bit map flag) indicative of validity/invalidity of each of the data included in each of the plural blocks, by using the block management table, and the controller updates the block management table, and changes the flag (bit map flag) corresponding to the data of the physical storage location corresponding to the block number and the in-block offset included in the Trim command to a value indicative of invalidity if the controller receives from the host the Trim command including the block number and the offset indicative of the physical storage location in which the data to be invalidated is stored).
Regarding claim 3, Yoshida discloses that retrieving the submap comprises: retrieving a submap zone count for the submap; and determining that the zone offset is not greater than the submap zone count, wherein retrieving the submap is in response to determining that the zone offset is not greater than the submap zone count ([0128], checks NSID included in the read request, read as determining that the zone offset is not greater than the submap zone count; and obtains the logical address from the received read request, and obtains the physical address corresponding to the obtained logical address from LUT (LUT for namespace #0) which manages mapping between each of the logical addresses corresponding to the namespace #0 and each of the physical addresses of the NAND flash memory 5).
Regarding claim 4, Yoshida discloses determining a submap zone offset by subtracting a previous submap zone count from the zone offset, wherein determining the physical address uses the submap and the submap zone offset ([0156], the read operation control unit 22 may first divide the in-block offset by the number of grains (4 in this case) indicative of the page size to obtain the physical storage location to be read).
Regarding claim 5, Yoshida discloses that the memory device comprises a plurality of superblocks (figure 18) and wherein retrieving the bitmap comprises: determining a superblock of the plurality of superblocks using the zone identifier; and retrieving the bitmap using the superblock ([0152], block number and the in-block offset can be used as the physical address for retrieving the bitmap).
Regarding claim 6, Yoshida discloses that the superblock includes data belonging to a plurality of zones and wherein determining the physical address comprises: determining a zone value using the zone identifier, wherein the zone value identifies data in the superblock belonging to the zone identifier; counting a number of zone values in the bitmap; determining that the counted number of zone values is equal to the zone offset; determining a bitmap location where the counted number of zone values is equal to the zone offset; and retrieving the physical address using the bitmap location ([0283]-[0289], one super block SB#1 is assumed to be composed of four blocks BLK#11, BLK#21, BLK#31, and BLK#41, and the controller (4) writes the data in order of page 0 of block BLK#11, page 0 of block BLK#21, page 0 of block BLK#31, page 0 of block BLK#41, as so on).
Regarding claim 7, Yoshida discloses determining the physical address comprises: counting a number of ones in the bitmap; determining that the counted number of ones is equal to the zone offset; determining a bitmap location where the counted number of one is equal to the zone offset; and retrieving the physical address using the bitmap location ([0128]-[0129], the controller (4) selects LBA API which is the API corresponding to the region #0 if the received read request includes NSID#0; and the controller (4) obtains physical address information designating a part of or all of the physical addresses from the received read request to read and access the designated namespace by using the physical address API).
Regarding claim 8, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 9, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 10, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 11, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 12, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Regarding claim 13, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 7.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 16, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claim 7.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bert (US 2024/0028231 A1) discloses a host system capable of placing write requests into separate streams and sending the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively (abstract and figure 5).
Frolikov (US 2019/0146927 A1) discloses an integration of processing and memory increases processing speed and memory transfer rate, and decreases latency and power usage comprising a controller to generate a first namespace map mapping according to a first block size, blocks of first logical addresses defined in a namespace to first blocks of second logical addresses defined for an entire capacity of the non-volatile storage media (abstract and figure 4).
Kavirayani et al. (US 2024/0094903 A1) discloses a controller configured to store, in a logical-to-physical (L2P) mapping table in the first volatile memory or the second volatile memory, a L2P address mapping of the logical address associated with the zone to a physical address associated with the first volatile memory or the non-volatile memory, the L2P address mapping being stored in response to the zone being an active zone (abstract and figure 1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
