Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/25/2026 have been fully considered but they are not persuasive. See the rejection below. If the applicants would have actually read the prior art and not just the relied on the examiner’s brief explanation it would have immediately been evident that the header and information (body) are both used together in the SCA messages.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kavala (US 2024/0295989, as listed on the IDS dated 6/26/2025.) in view of Hanna (US 2025/0118344).
In regards to claim 1, Kavala teaches
A memory system, comprising: (fig. 13, system 10)
a memory controller; (fig. 13, controller 200)
a buffer chip coupled to the memory controller; (fig. 13, FBI 110 (¶44 refers to it as an interface chip OR a buffer chip), coupled to controller 200 via CH)
a first group of memory devices, wherein a first data path is coupled between the buffer chip and the first group of memory devices; (fig. 13, top set of 4 NVMs (first group of memory devices) attached to ICH1 (first data path) which connects to FBI 110 (buffer chip))
a second group of memory devices, wherein a second data path is coupled between the buffer chip and the second group of memory devices, (fig. 13, bottom set of 4 NVMs (second group of memory devices) attached to ICH2 (second data path) which connects to FBI 100 (buffer chip)
the buffer chip is configured to control the first data path and the second data path based on control signaling received from the memory controller. (¶85-90 the controller controls the overall operations of the NVM package 100 and the interface (buffer) chip 110 converts/sends messages to the to the internal channels ICH1, ICH2 (first, second data path) according to signals received on the external channel CH between the controller 200 and the interface (buffer) chip 110
Kavala may not explicitly teach
determine a separate command address (SCA) message based on at least the control signaling received from the memory controller, the SCA message comprising a header and a body, and
in response to a determination that the header of the SCA message indicates a predetermined SCA message type, perform, based on the body of the SCA message, one of:
disabling the first data path and the second data path, enabling the first data path and disabling the second data path, disabling the first data path and enabling the second data path, or enabling the first data path and the second data path.
Kavala does teach in Fig. 1, 2 and 9, when the controller – buffer interface is in the NIF1 mode, the controller sends signals using the CLE (command latch enable) and ALE (address latch enable) pins to the FBI (buffer chip).
Hanna teaches in fig. 3 and ¶46-51 that an SCA message can be sent over the command/address pins CA0 and CA1 (equivalent to Kavala’s CLE and ALE), these SCA messages may have a header and a body, where the header data can indicate a chip select command and the following body can indicate which chip select lines to enable for a data transfer. As the chip selects are in the SCA message, the data paths (see Kavala fig. 13) to the NVM chips would be enable/disabled based upon the selected chips to be accessed, or both disabled if the SCA command wasn’t for accessing the chips.)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated the teachings of Hanna to improve the system of Kavala, as by using the CLE/ALE pins to send SCA messages that can contain chip select data (via a header and body), the CE[N:0] (chip select lines, see fig. 2 of Kavala) between the controller and the FBI (buffer chip) can be eliminated. The motivation for this, is that this simplifies the connections required between the controller and buffer chip, and also allows greater versatility, as the SCA messaging can be used for more than just chip selection.
In regards to claim 2, Kavala further teaches
wherein the buffer chip is configured to receive a first data signal from the memory controller and forward the first data signal to the first data path or the second data path without shaping the first data signal, and receive a second data signal from the first data path or the second data path and forward the second data signal to the memory controller without shaping the second data signal. (figs. 2, 7 and 8, ¶53-56 and ¶64-68, when the NVMs and controller are using the same protocol (i.e. NIF1 (legacy protocol) or NIF2 (SCA protocol) then the commands are passed through (without data shaping) the FBI (buffer chip) to the appropriate NVM devices (i.e. either the first/second data path) and appropriate responses returned from the accessed NVM devices to the controller via the same protocol (i.e. without data shaping)
In regards to claim 3, Kavala further teaches
wherein the buffer chip comprises a first group of data pins coupled to the first group of memory devices through the first data path, and a second group of data pins coupled to the second group of memory devices through the second data path, and the buffer chip is configured to forward a data signal from the memory controller to the first data path through the first group of data pins or to the second data path through the second group of data pins. (¶120, 143 figs. 17, 18 the buffer chip has data pins DQ_N connected to the memory chips. fig. 13, top set of 4 NVMs (first group of memory devices) attached to ICH1 (first data path, with DQ_N data pins) which connects to FBI 110 (buffer chip), bottom set of 4 NVMs (second group of memory devices) attached to ICH2 (second data path, with DQ_N pins) which connects to FBI 100 (buffer chip)
In regards to claim 4, Kavala further teaches
wherein the buffer chip further comprises a third group of data pins, first control pins, and second control pins, and wherein the third group of data pins, the first control pins, and the second control pins are coupled to the memory controller. (figs. 1-8, ¶54-56 teaches the sets of data (third group of data pins) and control pins (first and second control pins) connected between the controller and the interface buffer chip, and which are used during which modes of operation)
In regards to claim 5, Kavala further teaches
wherein the first control pins comprise a first chip enable pin coupled to the memory controller and the first group of memory devices, and a second chip enable pin coupled to the memory controller and the second group of memory devices, the second control pins comprise a command latch enable pin and an address latch enable pin, and the command latch enable pin and the address latch enable pin are coupled to the memory controller, the first group of memory devices, and the second group of memory devices. (figs. 1-8, ¶54-56 teaches chip enable (CE[N:0]) pins (i.e. first/second) for selecting which devices to enable (i.e. first/second memory devices). A ALE (address latch enable) pin and a CLE (command latch enable) pin. Fig. 8 shows that both the controller and NVM in a NIF1 mode that uses these pins.
In regards to claim 6, Kavala further teaches
wherein the buffer chip is configured to switch between a legacy mode and SCA mode based on a control signal from the memory controller. (¶54-56, fig. 2, teaches the SCA pin can be used to signal the activation between NIF1 (legacy) and NIF2 (SCA) modes of operation.
In regards to claim 7, Kavala further teaches
wherein the buffer chip is in the legacy mode, and the control signaling includes a first chip enable signal and a second chip enable signal received from the memory controller through the first chip enable pin and the second chip enable pin respectively. (fig. 2, ¶54-56, when in NIF1 (legacy mode) the CE[N:0] (i.e. first, second, etc) chip enable pins are used).
In regards to claim 8, Kavala further teaches
wherein the buffer chip is in the SCA mode, (fig. 1, 2, and 9, where the FBI (buffer chip) – NVM interface is in NIF2 mode (i.e. SCA mode) and the controller – FBI (buffer chip) is in the NIF1 mode)
the control signaling includes a command latch enable signal and an address latch enable signal received from the memory controller through the command latch enable pin and the address latch enable pin respectively, (Fig. 1, 2 and 9, when the controller – buffer interface is in the NIF1 mode, the controller sends signals using the CLE (command latch enable) and ALE (address latch enable) pins to the FBI (buffer chip)
Hanna further teaches
and the buffer chip is configured to determine an SCA message based on at least the command latch enable signal, the address latch enable signal, and an SCA protocol. (Hanna teaches in fig. 3 and ¶46-51 that an SCA message can be sent over the command/address pins CA0 and CA1 (equivalent to Kavala’s CLE and ALE), these SCA messages may have a header and a body, where the header data can indicate which chip select lines to enable for a data transfer.)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated the teachings of Hanna to improve the system of Kavala, as by using the CLE/ALE pins to send SCA messages that can contain chip select data, the CE[N:0] (chip select lines, see fig. 2 of Kavala) between the controller and the FBI (buffer chip) can be eliminated. The motivation for this, is that this simplifies the connections required between the controller and buffer chip, and also allows greater versatility, as the SCA messaging can be used for more than just chip selection.
In regards to claim 10, Kavala teaches
wherein the buffer chip comprises: a first circuit coupled to the first control pins and the second control pins; (fig. 16, CMD 1111)
a second circuit coupled to the first group of data pins, the second group of data pins, and the third group of data pins, (fig. 16, Muxs 1114-1116)
Kavala may not explicitly teach
wherein the first circuit is configured to operate in a first voltage domain, and the second circuit is configured to operate in a second voltage domain.
However, ¶179 of Kavala suggests that operation of circuit devices can differ, therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have these two circuits operate in a first/second voltage domain. The motivation for this modification is that different circuits may require different voltages to operate effectively and efficiently, as mentioned in ¶179, page (data) buffer circuits may require a higher voltage than decoder (i.e. command) circuits.
In regards to claim 11, Kavala teaches
wherein the second circuit comprises: a first group of switches coupled between the first group of data pins and the third group of data pins; and a second group of switches coupled between the second group of data pins and the third group of data pins. (fig. 16, Muxs (i.e. switches) 1114-1116)
In regards to claim 12, Kavala further teaches
wherein the first group of memory devices comprises four memory devices, and the second group of memory devices comprises four memory devices. ( fig. 13, top set of 4 NVMs (first group of memory devices) attached to ICH1 (first data path, with DQ_N data pins) which connects to FBI 110 (buffer chip), bottom set of 4 NVMs (second group of memory devices) attached to ICH2 (second data path, with DQ_N pins) which connects to FBI 100 (buffer chip)
In regards to claim 13, 14, 16, 17 and 20, the claims are similar in scope the claims addressed above and are rejected for the same reasons.
In regards to claims 15, 18-19, they are similar in scope to claim 8 above and are therefore rejected for the same reasons as indicated above.
In regards to claim 21, Hanna further teaches
wherein the header includes four bits (p49 teaches the header may be 4 bits)
Kavala and/or Hanna may not explicitly teach
and the body includes eight bits, wherein first four bits of the body represents a first operation code and last four bits of the body represents a second operation code, and wherein the first operation code is defined as an operation type and the second operation code is defined as a specific operation command.
However, Hanna does teach in p46-47 and fig. 3, that the information 330 (i.e. body) can be used to communicate configuration, command, and/or data related to the header.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to use as many bits as needed in the body (information) as required by the associated header(s) in order to define a command (i.e. opcodes), such as a first 4 bits for a opcode and the last 4 bits for another opcode. The motivation for such is that this is strictly a design implementation based on the system design and the SCA interface, which would be well within the knowledge and skill of one of ordinary skill in the art to implement, and have been able to achieve predictable results. Note: simply defining the number of bits and meaning of such bits in messages is not inventive and completely obvious as it is the basic foundation of digital communications that is required for anything to work and communicate correctly.
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The applicant is reminded of what constitutes a proper reply to this office action is detailed in 37 CFR 1.111, and that the examiner has the discretion to treat any response that fails to meet ALL the requirements of that section as NON-RESPONSIVE without any additional extensions of time (see MPEP 714.03).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON W BLUST/Primary Examiner, Art Unit 2132
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