Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4-5 are rejected under U.S.C. 103 as being unpatentable over Schneider et al. (US Pat. Pub. 20070051949; hereinafter referred to as Schneider) in view of Cho et al. (US Pat. Pub. 20250260420; filed 8/16/2024; hereinafter referred to as Cho).
As per claim 1:
Schneider teaches a test circuit (Schneider par. 0013, stacked multiple die semiconductor device 100), comprising: an output control circuit (Schneider par. 0014, each chip contains its own test mode output control circuit) configured to select one of the plurality of test result signals and the read data in accordance with die identification information and a test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information) and configured to sequentially output the selected signal through a preassigned pad, among a plurality of pads (Schneider par. 0018, each test mode output control circuit selectively routes the test result to its DQ0 or DQ1).
Schneider does not explicitly disclose a data compression circuit configured to compress read data transmitted through a plurality of first signal lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of second signal lines. However, Cho discloses a data compression circuit configured to compress read data transmitted through a plurality of first signal lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of second signal lines (Cho par. 0068, plurality of compression engines, interpreted as a compression circuit, transmits data through a plurality of local data lines. Please note the compression engines compress soft decision data as stated in Cho par. 0047).
Schneider and Cho are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho’s local data lines and global data lines with the apparatus of Schneider. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it enhances the performance of the non-volatile memory and decreases the timing interval for occupying channels (Cho par. 0007).
As per claim 4:
Schneider teaches a semiconductor apparatus (Schneider par. 0013, stacked multiple die semiconductor device 100), comprising: an output control circuit (Schneider par. 0014, each chip contains its own test mode output control circuit) configured to select one of the plurality of test result signals and the read data in accordance with die identification information and a test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information) and configured to sequentially output the selected signal through a preassigned pad, among a plurality of pads (Schneider par. 0018, each test mode output control circuit selectively routes the test result to its DQ0 or DQ1).
Schneider does not explicitly disclose a plurality of unit memory regions; a plurality of normal global lines coupled in common with the plurality of unit memory regions; a data compression circuit configured to compress read data transmitted through the plurality of normal global lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of test global lines. However, Cho discloses a plurality of unit memory regions; a plurality of normal global lines coupled in common with the plurality of unit memory regions (Cho par. 0069, a plurality of global data lines coupled to page buffer circuits. Please note the page buffer circuits are coupled to plurality of memory planes as stated in Cho par. 0067); a data compression circuit configured to compress read data transmitted through the plurality of normal global lines to generate a plurality of test result signals and configured to output the plurality of test result signals through a plurality of test global lines (Cho par. 0068, plurality of compression engines, interpreted as a compression circuit, transmits data through a plurality of local data lines. Please note the compression engines compress soft decision data as stated in Cho par. 0047).
Schneider and Cho are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho’s local data lines and global data lines with the apparatus of Schneider. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it enhances the performance of the non-volatile memory and decreases the timing interval for occupying channels (Cho par. 0007).
As per claim 5:
Schneider and Cho further teach the semiconductor apparatus of claim 4, wherein the data compression circuit is configured to output a signal compressing read data output from one of the plurality of unit memory regions as one of the plurality of test result signals (Cho Fig. 3, soft decision data output from memory planes 210-240 is compressed and output as compressed soft decision data CPR_SD).
Claims 2-3 and 6-7 are rejected under U.S.C. 103 as being unpatentable over Schneider-Cho in further view of An (US Pat. Pub. 20070294462).
As per claim 2:
Schneider and Cho further teach the test circuit of claim 1, wherein the output control circuit includes a plurality of control units (Schneider par. 0014, each chip contains its own test mode output control circuit).
Schneider and Cho do not explicitly disclose configured to multiplex some bits of the read data and one of the plurality of test result signals according to the die identification information and the test mode signal. However, An discloses configured to multiplex some bits of the read data and one of the plurality of test result signals according to the die identification information and the test mode signal (An Fig. 2 and par. 0077, plurality of multiplexers to output a signal from the global input/output driver or data output driver).
Schneider, Cho and An are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine An’s multiplexers with the apparatus of Schneider-Cho because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for resource sharing as a single output line can be shared among multiple inputs.
As per claim 3:
Schneider, Cho, and An further teach the test circuit of claim 2, wherein each of the plurality of control units comprises: a decoding circuit configured to generate a plurality of selection signals according to the die identification information and the test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information. Please note decoder circuits are located in the test mode output control circuits as stated in Schneider par. 0020); and a multiplexing circuit configured to select and output one of each of the some bits of the read data and one of the plurality of test result signals according to the plurality of selection signals (An Fig. 2 and par. 0077).
As per claim 6:
Schneider and Cho further teach the semiconductor apparatus of claim 4, wherein the output control circuit includes a plurality of control units (Schneider par. 0014, each chip contains its own test mode output control circuit).
Schneider and Cho do not explicitly disclose configured to multiplex some bits of the read data and one of the plurality of test result signals according to the die identification information and the test mode signal. However, An discloses configured to multiplex some bits of the read data and one of the plurality of test result signals according to the die identification information and the test mode signal (An Fig. 2 and par. 0077, plurality of multiplexers to output a signal from the global input/output driver or data output driver).
Schneider, Cho and An are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine An’s multiplexers with the apparatus of Schneider-Cho because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for resource sharing as a single output line can be shared among multiple inputs.
As per claim 7:
Schneider, Cho, and An further teach the semiconductor apparatus of claim 6, wherein each of the plurality of control units comprises: a decoding circuit configured to generate a plurality of selection signals according to the die identification information and the test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information. Please note decoder circuits are located in the test mode output control circuits as stated in Schneider par. 0020); and a multiplexing circuit configured to select and output one of each of the some bits of the read data and one of the plurality of test result signals according to the plurality of selection signals (An Fig. 2 and par. 0077).
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Schneider in view of Lai et al. (US Pat. Pub. 20080308947; hereinafter referred to as Lai).
As per claim 8:
Schneider teaches a semiconductor apparatus, comprising a plurality of semiconductor dies (Schneider par. 0013, stacked multiple die/chip semiconductor device 100), each having a plurality of pads (Schneider par. 0016, each chip is connected to DQ pins) and configured such that when a test read command is input, the plurality of semiconductor dies simultaneously output test results through some of the plurality of pads in different order (Schneider par. 0022, supply test mode signals to each chip to initiate a test mode procedure simultaneously on two or more chips. Please note this results in the test results output simultaneously as stated in Schneider par. 0007).
Schneider does not explicitly disclose a plurality of pads coupled to each other through bonding wires. However, Lai discloses a plurality of pads coupled to each other through bonding wires (Lai par. 0028, wire bonding is used to connect bond pads on the die).
Schneider and Lai are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lai’s wire bonding used to connect bond pads with the apparatus of Schneider. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it improves the yield of manufactured devices (Lai par. 0026).
Claims 9 and 12-14 are rejected under U.S.C. 103 as being unpatentable over Schneider-Lai in further view of Cho
As per claim 9:
Schneider and Lai further teach the semiconductor apparatus of claim 8, wherein each of the plurality of semiconductor dies includes an output control circuit (Schneider par. 0014, each chip contains its own test mode output control circuit) configured to select signals (Schneider par. 0018, each test mode output control circuit selectively routes the test result to its DQ0 or DQ1) transmitted in accordance with die identification information and a test mode signal and configured to output the selected signals through one of the some pads (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information).
Schneider and Lai do not explicitly disclose through one of a plurality of test global lines and a plurality of normal global lines. However, Cho discloses through one of a plurality of test global lines (Cho par. 0081-0082, transmit compressed soft decision data through one of the local data lines) and a plurality of normal global lines (Cho par. 0082-0083, transmit data through global data lines separate from the local data lines).
Schneider, Lai, and Cho are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho’s local data lines and global data lines with the apparatus of Schneider-Lai. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it enhances the performance of the non-volatile memory and decreases the timing interval for occupying channels (Cho par. 0007).
As per claim 12:
Schneider and Lai further teach the semiconductor apparatus of claim 8, wherein each of the plurality of semiconductor dies includes: an output control circuit (Schneider par. 0014, each chip contains its own test mode output control circuit), and wherein, when the test read command is input, an output control circuit of a first semiconductor die, which is the lowermost among the plurality of semiconductor dies, is configured to output the plurality of test result signals through a first pad of the plurality of pads, and an output control circuit of a second semiconductor die stacked on the first semiconductor die (Schneider par. 0013, chips 110 and 120 are stacked on each other. Please note chip 120 is the lowermost die and chip 110 is the second semiconductor die stacked on the first as seen in Schneider Fig. 2) is configured to output the plurality of test result signals through a second pad of the plurality of pads simultaneously (Schneider par. 0007 the test results output simultaneously. Please note one of the chips is configured to output its test results to pad DQ0 and the other is configured to output its test results to pad DQ1 as stated in Schneider par. 0016).
Schneider and Lai do not explicitly disclose a plurality of normal global lines coupled in common with a plurality of unit memory regions; a data compression circuit configured to output a plurality of test result signals through a plurality of test global lines generated by compressing read data transmitted through the plurality of normal global lines. However, Cho discloses a plurality of normal global lines coupled in common with a plurality of unit memory regions (Cho par. 0069, a plurality of global data lines coupled to page buffer circuits. Please note the page buffer circuits are coupled to plurality of memory planes as stated in Cho par. 0067); a data compression circuit configured to output a plurality of test result signals through a plurality of test global lines generated by compressing read data transmitted through the plurality of normal global lines (Cho par. 0068, plurality of compression engines, interpreted as a compression circuit, transmits data through a plurality of local data lines. Please note the compression engines compress soft decision data as stated in Cho par. 0047).
Schneider, Lai, and Cho are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cho’s local data lines and global data lines with the apparatus of Schneider-Lai. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it enhances the performance of the non-volatile memory and decreases the timing interval for occupying channels (Cho par. 0007).
As per claim 13:
Schneider, Lai, and Cho further teach the semiconductor apparatus of claim 12, wherein, when a normal read command is input, an output control circuit of one of the plurality of semiconductor dies is configured to output read data transmitted through the plurality of normal global lines to the plurality of pads (Cho par. 0046, perform a read operation. Please note read data is transmitted through global data lines to input/output data pads as stated in Cho par. 0141).
As per claim 14:
Schneider, Lai, and Cho further teach the semiconductor apparatus of claim 12, wherein the data compression circuit is configured to output a signal compressing read data output from one of the plurality of unit memory regions as one of the plurality of test result signals (Cho Fig. 3, soft decision data output from memory planes 210-240 is compressed and output as compressed soft decision data CPR_SD).
Claims 10-11 are rejected under U.S.C. 103 as being unpatentable over Schneider-Lai in further view of An.
As per claim 10:
Schneider and Lai further teach the semiconductor apparatus of claim 8, each of the plurality of semiconductor dies includes a plurality of control units (Schneider par. 0014, each chip contains its own test mode output control circuit).
Schneider and Lai do not explicitly disclose configured to multiplex and output a first set of signals transmitted through some of a plurality of normal global lines and a second signal transmitted through one of a plurality of test global lines, according to die identification information and a test mode signal. However, An discloses configured to multiplex and output a first set of signals transmitted through some of a plurality of normal global lines and a second signal transmitted through one of a plurality of test global lines, according to die identification information and a test mode signal (An Fig. 2 and par. 0077, plurality of multiplexers to output a signal from the global input/output driver or data output driver).
Schneider, Lai, and An are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine An’s multiplexers with the apparatus of Schneider-Lai because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for resource sharing as a single output line can be shared among multiple inputs.
As per claim 11:
Schneider, Lai, and An further teach the semiconductor apparatus of claim 10, wherein each of the plurality of control units comprises: a decoding circuit configured to generate a plurality of selection signals based on the die identification information and the test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information. Please note decoder circuits are located in the test mode output control circuits as stated in Schneider par. 0020); and a multiplexing circuit configured to select and output one of each of the first set of signals and the second signal according to the plurality of selection signals (An Fig. 2 and par. 0077).
Claims 15-16 are rejected under U.S.C. 103 as being unpatentable over Schneider-Lai-Cho in further view of An.
As per claim 15:
Schneider, Lai, and Cho further teach the semiconductor apparatus of claim 12, wherein the output control circuit includes a plurality of control units (Schneider par. 0014, each chip contains its own test mode output control circuit).
Schneider, Lai, and Cho do not explicitly disclose configured to multiplex some bits of the read data and one of the plurality of test result signals according to die identification information and a test mode signal. However, An discloses configured to multiplex some bits of the read data and one of the plurality of test result signals according to die identification information and a test mode signal (An Fig. 2 and par. 0077, plurality of multiplexers to output a signal from the global input/output driver or data output driver).
Schneider, Lai, Cho and An are analogous arts because they are in the same field of endeavor of semiconductors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine An’s multiplexers with the apparatus of Schneider-Lai-Cho because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for resource sharing as a single output line can be shared among multiple inputs.
As per claim 16:
Schneider, Lai, Cho, and An further teach the semiconductor apparatus of claim 15, wherein each of the plurality of control units comprises: a decoding circuit configured to generate a plurality of selection signals according to the die identification information and the test mode signal (Schneider par. 0016-0017, respective test mode output control signal corresponds to a test mode output control circuit, which acts as chip identification information. Please note decoder circuits are located in the test mode output control circuits as stated in Schneider par. 0020); and a multiplexing circuit configured to select and output one of each of the some bits of the read data and one of the plurality of test result signals according to the plurality of selection signals (An Fig. 2 and par. 0077).
Conclusion
The additional prior arts made of record and have not been relied upon are considered pertinent to applicant’s disclosure as follows:
Ku (US Pat. Pub. 20140133247) discloses a semiconductor memory device including a compression unit configured to compress a plurality of data, which are read from a memory cell region.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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