CTNF 19/071,301 CTNF 81571 DETAILED ACTION The following is an initial Office Action upon examination of the above-identified application on the merits. Claims 1-20 are pending in this application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-49-07 The information disclosure statement filed 25 April 2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication (“Search Report Received for Taiwan Application No. 103127660, dated 01 November 2021, 1 Page.”) or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. 06-49 AIA The information disclosure statement filed 25 April 2025 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because Taiwan Patent Publication No. TWM 481918 is illegible . It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a). Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12,265,380 B2 (hereinafter Moyne2) . Although the claims at issue are not identical, they are not patentably distinct from each other because they claim common subject matter as follows: Instant Application No. 19/071,301 (hereinafter Moyne) U.S. Patent No. 12,265,380 B2 (hereinafter Moyne2) 1. A method comprising: generating composite input parameters using first input parameters of a first processing chamber associated with a first process run and second input parameters of a second processing chamber associated with a second process run; generating third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters; generating fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters; and causing fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run; and causing fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run. 1. A method comprising: identifying first parameters of a first processing chamber of a semiconductor fabrication facility, the first parameters comprising first input parameters and first output parameters; identifying second parameters of a second processing chamber of the semiconductor fabrication facility, the second parameters comprising second input parameters and second output parameters; generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters comprising process conditions and composite output parameters comprising metrology values; generating third parameters by adjusting the first parameters , wherein the third parameters more closely approximate the composite parameters than the first parameters; generating fourth parameters by adjusting the second parameters , wherein the fourth parameters more closely approximate the composite parameters than the second parameters; and fabricating first semiconductors in the first processing chamber based on the third parameters and fabricating second semiconductors in the second processing chamber based on the fourth parameters, wherein the fabricating of the first semiconductors in the first processing chamber based on the third parameters corresponds to lower yield loss than corresponding fabrication of corresponding semiconductors in the first processing chamber based on the first parameters, and the fabricating of the second semiconductors in the second processing chamber based on the fourth parameters corresponds to lower yield loss than respective fabrication of respective semiconductors in the second processing chamber based on the second parameters. 2. The method of claim 1, further comprising: subsequent to the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors, generating second composite input parameters using the third input parameters and the fourth input parameters, wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters . 2. The method of claim 1 further comprising: responsive to the fabricating of the first semiconductors, identifying updated third parameters; and updating, based on the updated third parameters , at least a portion of the composite parameters to generate updated composite parameters , wherein subsequent fabrication of semiconductors via at least the first and second processing chambers is based on the updated composite parameters . The method of claim 1, wherein the generating of the composite input parameters comprises averaging the first input parameters and the second input parameters, the composite input parameters being an average recipe. 3. The method of claim 1, wherein the generating of the composite parameters comprises averaging the first input parameters of the first processing chamber and the second input parameters of the second processing chamber to determine the composite input parameters, wherein the composite input parameters is an average recipe. The method of claim 1, wherein a first model of the first processing chamber is based on the first input parameters and a second model of the second processing chamber is based on the second input parameters, and wherein generating the composite input parameters comprises: averaging the first model and the second model to generate a composite model, wherein the composite model is associated with the composite input parameters. 4. The method of claim 1, wherein a first model of the first processing chamber is based on the first parameters, wherein a second model of the second processing chamber is based on the second parameters, and wherein the generating of the composite parameters comprises: averaging the first model and the second model to generate a composite model, wherein the composite model is associated with the composite parameters. The method of claim 4, further comprising: inverting the composite model to determine an average recipe, wherein the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors are based on the average recipe. 5. The method of claim 4, further comprising: inverting the composite model to determine an average recipe, wherein the fabricating of the first semiconductors and the fabricating of the second semiconductors is based on the average recipe. The method of claim 1, further comprising: weighting at least one parameter of the first input parameters or the second input parameters, wherein the composite input parameters are generated based on the weighting of the at least one parameter. 6. The method of claim 1, further comprising weighting at least one parameter of one or more of the first parameters or the second parameters, wherein the generating of the composite parameters is further based on the weighting of the at least one parameter. The method of claim 1, wherein the generating of the composite input parameters comprises matching the first input parameters and the second input parameters. 7. The method of claim 1, wherein the generating of the composite parameters comprises matching the first input parameters and the second input parameters. A non-transitory computer-readable storage medium, the computer-readable storage medium storing instructions that when executed by one or more processing devices, cause the one or more processing devices to: generate composite input parameters using first input parameters of a first processing chamber associated with a first process run and second input parameters of a second processing chamber associated with a second process run; generate third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters; generate fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters; and cause fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run; and cause fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run. 8. A non-transitory machine-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying first parameters of a first processing chamber of a semiconductor fabrication facility, the first parameters comprising first input parameters and first output parameters; identifying second parameters of a second processing chamber of the semiconductor fabrication facility, the second parameters comprising second input parameters and second output parameters; generating, based on the first parameters and the second parameters, composite parameters comprising composite input parameters comprising process conditions and composite output parameters comprising metrology values; generating third parameters by adjusting the first parameters , wherein the third parameters more closely approximate the composite parameters than the first parameters; generating fourth parameters by adjusting the second parameters , wherein the fourth parameters more closely approximate the composite parameters than the second parameters; and fabricating first semiconductors in the first processing chamber based on the third parameters and fabricating second semiconductors in the second processing chamber based on the fourth parameters, wherein the fabricating of the first semiconductors in the first processing chamber based on the third parameters corresponds to lower yield loss than corresponding fabrication of corresponding semiconductors in the first processing chamber based on the first parameters, and the fabricating of the second semiconductors in the second processing chamber based on the fourth parameters corresponds to lower yield loss than respective fabrication of respective semiconductors in the second processing chamber based on the second parameters. The computer-readable storage medium of claim 8, wherein the instructions further configure the one or more processing devices to: subsequent to causing the fabrication of the first semiconductors and causing the fabrication of the second semiconductors, generate second composite input parameters using the third input parameters and the fourth input parameters, wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters . 9. The non-transitory machine-readable storage medium of claim 8, the operations further comprising: responsive to the fabricating of the first semiconductors based on the third parameters, identifying updated third parameters; and updating, based on the updated third parameters , at least a portion of the composite parameters to generate updated composite parameters , wherein subsequent fabrication of semiconductors via at least the first and second processing chambers is based on the updated composite parameters . The computer-readable storage medium of claim 8, wherein to generate the composite input parameters, the one or more processing devices are to: average the first input parameters and the second input parameters, the composite input parameters being an average recipe. 10. The non-transitory machine-readable storage medium of claim 8, wherein the generating of the composite parameters comprises averaging the first input parameters of the first processing chamber and the second input parameters of the second processing chamber to determine the composite input parameters, wherein the composite input parameters is an average recipe. The computer-readable storage medium of claim 8, wherein a first model of the first processing chamber is based on the first input parameters and a second model of the second processing chamber is based on the second input parameters, and wherein to generate the composite input parameters, the one or more processing devices are to: average the first model and the second model to generate a composite model, wherein the composite model is associated with the composite input parameters. 11. The non-transitory machine-readable storage medium of claim 8, wherein a first model of the first processing chamber is based on the first parameters, wherein a second model of the second processing chamber is based on the second parameters, wherein the generating of the composite parameters comprises averaging the first model and the second model to generate a composite model, and wherein the composite model is associated with the composite parameters. 12. The computer-readable storage medium of claim 11, wherein the one or more processing devices are to: invert the composite model to determine an average recipe, wherein causing the fabrication of the first semiconductors and causing the fabrication of the second semiconductors are based on the average recipe. The non-transitory machine-readable storage medium of claim 11, the operations further comprising inverting the composite model to determine an average recipe, wherein the fabricating of the first semiconductors and the fabricating of the second semiconductors is based on the average recipe. The computer-readable storage medium of claim 8, wherein the one or more processing devices are further to: weight at least one parameter of the first input parameters or the second input parameters, wherein the composite input parameters are generated based on weighting of the at least one parameter. 13. The non-transitory machine-readable storage medium of claim 8, the operations further comprising w weighting at least one parameter of one or more of the first parameters or the second parameters, wherein the generating of the composite parameters is further based on the weighting of the at least one parameter. The computer-readable storage medium of claim 8, wherein to generate the composite input parameters, the one or more processing devices are to: match the first input parameters and the second input parameters. 14. The non-transitory machine-readable storage medium of claim 8, wherein the generating of the composite parameters comprises matching the first input parameters and the second input parameters. A system comprising: a memory; and one or more processors coupled to the memory, the one or more processors to: generate composite input parameters using first input parameters of the first processing chamber associated with a first process run and second input parameters of the second processing chamber associated with a second process run; generate third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters; generate fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters; and cause fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run; and cause fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run. 15. A system comprising: a memory; and a processing device coupled to the memory, the processing device to: identify first parameters of a first processing chamber of a semiconductor fabrication facility, the first parameters comprising first input parameters and first output parameters; identify second parameters of a second processing chamber of the semiconductor fabrication facility, the second parameters comprising second input parameters and second output parameters; generate, based on the first parameters and the second parameters, composite parameters comprising composite input parameters associated with process conditions and composite output parameters associated with metrology values; generate third parameters by adjusting the first parameters , wherein the third parameters more closely approximate the composite parameters; generate fourth parameters by adjusting the second parameters to more closely approximate the composite parameters; and fabricate first semiconductors in the first processing chamber based on the third parameters and fabricate second semiconductors in the second processing chamber based on the fourth parameters, wherein fabricating the first semiconductors in the first processing chamber based on the third parameters corresponds to lower yield loss than corresponding fabrication of corresponding semiconductors in the first processing chamber based on the first parameters, and fabricating of the second semiconductors in the second processing chamber based on the fourth parameters corresponds to lower yield loss than respective fabrication of respective semiconductors in the second processing chamber based on the second parameters. The system of claim 15, wherein the instructions further configure the system to: subsequent to causing the fabrication of the first semiconductors and causing the fabrication of the second semiconductors, generate second composite input parameters using the third input parameters and the fourth input parameters, wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters. The system of claim 15, wherein the processing device is further to: responsive to fabricating the first semiconductors based on the third parameters, identify updated third parameters; and update, based on the updated third parameters , at least a portion of the composite parameters to generate updated composite parameters , wherein subsequent fabrication of semiconductors via at least the first and second processing chambers is based on the updated composite parameters . 17. The system of claim 15, wherein to generate the composite input parameters, the one or more processing devices are to: average the first input parameters and the second input parameters, the composite input parameters being an average recipe. 17. The system of claim 15, wherein to generate the composite parameters, the processing device is to average the first input parameters of the first processing chamber and the second input parameters of the second processing chamber to determine the composite input parameters, wherein the composite input parameters is an average recipe. 18. The system of claim 15, wherein a first model of the first processing chamber is based on the first input parameters and a second model of the second processing chamber is based on the second input parameters, and wherein to generate the composite input parameters, the one or more processors to: average the first model and the second model to generate a composite model, wherein the composite model is associated with the composite input parameters. The system of claim 15, wherein a first model of the first processing chamber is based on the first parameters, wherein a second model of the second processing chamber is based on the second parameters, wherein; and to generate the composite parameters, the processing device is to average the first model and the second model to generate a composite model, and wherein the composite model is associated with the composite parameters. The system of claim 18, wherein the one or more processors are to: invert the composite model to determine an average recipe, wherein causing the fabrication of the first semiconductors and causing the fabrication of the second semiconductors are based on the average recipe. 19. The system of claim 18, wherein the processing device is further to invert the composite model to determine an average recipe, wherein the fabricating of the first semiconductors and the fabricating of the second semiconductors is based on the average recipe. The system of claim 15, wherein the one or more processors are further to: weight at least one parameter of the first input parameters or the second input parameters, wherein the composite input parameters are generated based on weighting of the at least one parameter. 20. The system of claim 15, wherein the processing device is further to weight at least one parameter of one or more of the first parameters or the second parameters, wherein the processing device is to generate the composite parameters further based on weighting of the at least one parameter. In summary, claims 1-20 are unpatentable as being anticipated by claims 1-20 of Moyne2 as represented by the direct correlation of Moyne with Moyne2 as set forth above . Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1: At step 1, the recites a method for comprising of a plurality of “actions”; and therefore is a process, which is a statutory category of invention. At step 2A, prong one the claim recites “generating composite input parameters using first input parameters of a first processing chamber associated with a first process run and second input parameters of a second processing chamber associated with a second process run”; “generating third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters”; and “generating fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters”. The limitation of “generating composite input parameters using first input parameters of a first processing chamber associated with a first process run and second input parameters of a second processing chamber associated with a second process run” (U.S. Patent Publication No. 2025/0199521 A1: pgs. 2-3, par. [0028]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. The limitation of “generating third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters”, as drafted, is a process, under its broadest reasonable interpretation covers performing the limitation by use of steps in organizing a human activit(ies). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations by managing personal behavior (i.e. “generating third input parameters by adjusting the first input parameters …”) using an instruction or rule (i.e. “… such that the third input parameters more closely approximate the composite input parameters than the first input parameters”), then it falls within the sub-grouping of “C. Managing Personal Behavior or Relationships or Interactions Between People” of the “Certain Methods of Organizing Human Activity” grouping of abstract ideas. (MPEP 2106.04(a)(2)(C)(II): “Finally, the sub-groupings encompass both activity of a single person (for example, a person following a set of instructions or a person signing a contract online) and activity that involves multiple people (such as a commercial interaction), and thus, certain activity between a person and a computer (for example a method of anonymous loan shopping that a person conducts using a mobile phone) may fall within the "certain methods of organizing human activity" grouping. It is noted that the number of people involved in the activity is not dispositive as to whether a claim limitation falls within this grouping. Instead, the determination should be based on whether the activity itself falls within one of the sub-groupings.”) Accordingly, the claim recites an abstract idea. The limitation of “generating fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters”, as drafted, is a process, under its broadest reasonable interpretation covers performing the limitation by use of steps in organizing a human activit(ies). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations by managing personal behavior (i.e. “generating fourth input parameters by adjusting the second input parameters …”) using an instruction or rule (i.e. “… such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters”), then it falls within the sub-grouping of “C. Managing Personal Behavior or Relationships or Interactions Between People” of the “Certain Methods of Organizing Human Activity” grouping of abstract ideas. (MPEP 2106.04(a)(2)(C)(II): “Finally, the sub-groupings encompass both activity of a single person (for example, a person following a set of instructions or a person signing a contract online) and activity that involves multiple people (such as a commercial interaction), and thus, certain activity between a person and a computer (for example a method of anonymous loan shopping that a person conducts using a mobile phone) may fall within the "certain methods of organizing human activity" grouping. It is noted that the number of people involved in the activity is not dispositive as to whether a claim limitation falls within this grouping. Instead, the determination should be based on whether the activity itself falls within one of the sub-groupings.”) Accordingly, the claim recites an abstract idea. At step 2A, prong two, the judicial is not integrated into a practical application. In particular, the claim recites “causing fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run”; and “causing fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run”. The limitations of “… first semiconductors in the first processing chamber in a third process run …”; and “… second semiconductors in the second processing chamber …” are generally recited at a high level of generality and merely limits the abstract idea to a field of use. The courts have found “a claim directed to a judicial exception cannot be made eligible ‘simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use.’ Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application.” (MPEP 2106.05(h)). The limitation of “ causing fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run” is a recitation of the words “apply it” (or an equivalent). “As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do "‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’". Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965).” (see MPEP 2106.05(f)) The limitation of “ causing fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run” is a recitation of the words “apply it” (or an equivalent). “As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do "‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’". Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965).” (see MPEP 2106.05(f)) Accordingly, these additional elements neither individually nor in combination integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the limitations of “… first semiconductors in the first processing chamber in a third process run …”; and “… second semiconductors in the second processing chamber …”, as discussed above, merely limit the abstract idea to a field of use. Wherein, limiting the invention to a field of use cannot provide an inventive concept. Thus, the claim is not patent eligible. (MPEP 2106.05(h)). The limitation of “ causing fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters, wherein the third process run corresponds to a lower yield loss than the first process run” represents an equivalent recitation of the phrase “apply it”, wherein the courts have identified limitations that “(m)erely recit(e) the words ‘apply it’ (or an equivalent)” with the judicial exception cannot provide an inventive concept …”. (see MPEP 2106.04(d)(I)). The limitation of “ causing fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters, wherein the fourth process run corresponds to a lower yield loss than the second process run” represents an equivalent recitation of the phrase “apply it”, wherein the courts have identified limitations that “(m)erely recit(e) the words ‘apply it’ (or an equivalent)” with the judicial exception cannot provide an inventive concept …”. (see MPEP 2106.04(d)(I)). Considering the additional elements individually and in combination and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 2: At step 2A, prong one the claim recites “subsequent to the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors, generating second composite input parameters using the third input parameters and the fourth input parameters …”. The limitation of “subsequent to the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors, generating second composite input parameters using the third input parameters and the fourth input parameters …” (U.S. Patent Publication No. 2025/0199521 A1: pgs. 2-3, par. [0028]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A, prong two, the judicial is not integrated into a practical application. In particular, the claim recites “… wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters”. The limitation of “… wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters” is a recitation of the words “apply it” (or an equivalent). “As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do "‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’". Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965).” (see MPEP 2106.05(f)) Accordingly, the additional element does not individually integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the limitation of “… wherein subsequent fabrication of semiconductors via the first processing chamber and the second processing chamber is based on the second composite input parameters”, as discussed above, represents an equivalent recitation of the phrase “apply it”, wherein the courts have identified limitations that “(m)erely recit(e) the words ‘apply it’ (or an equivalent)” with the judicial exception cannot provide an inventive concept …”. (see MPEP 2106.04(d)(I)). Considering the additional element individually and the claim as a whole, the additional element does not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 3: At step 2A, prong one the claim recites “… the generating of the composite input parameters comprises averaging the first input parameters and the second input parameters, the composite input parameters being an average recipe”. The limitation of “… the generating of the composite input parameters comprises averaging the first input parameters and the second input parameters, the composite input parameters being an average recipe” (U.S. Patent Publication No. 2025/0199521 A1: pgs. 2-3, par. [0028]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Claim 4: At step 2A, prong one, the claim recites “… generating the composite input parameters comprises: averaging the first model and the second model to generate a composite model, wherein the composite model is associated with the composite input parameters”. The limitation of “… generating the composite input parameters comprises: averaging the first model and the second model to generate a composite model, wherein the composite model is associated with the composite input parameters” (U.S. Patent Publication No. 2025/0199521 A1: pgs. 2-3, par. [0028]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A, prong two, the judicial exception is not integrated into a practical application. In particular, the claim recites “… a first model of the first processing chamber is based on the first input parameters …” and “… a second model of the second processing chamber is based on the second input parameters”. The limitations of “… a first model of the first processing chamber is based on the first input parameters …” and “… a second model of the second processing chamber is based on the second input parameters” represent data gathering that is necessary for use in the recited judicial exception, as the models are used in the abstract process of generating a composite model. The models are recited at a high level of generality and recited so generically they represent no more than an insignificant extra-solution activity of gathering data. (see MPEP 2106.05(g)) Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limitations on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the limitations “… a first model of the first processing chamber is based on the first input parameters …” and “… a second model of the second processing chamber is based on the second input parameters”, as discussed above, represent an insignificant extra-solution activity of data gathering. Further, the limitations are well-understood, routine and conventional; wherein the courts have found limitations directed to obtaining data, recited at a high level of generality, to be well-routine, and conventional. See MPEP 2106.05(d)(II), “storing and retrieving information in memory”. Considering the additional elements individually and in combination and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 5: At step 2A, prong one, the claim recites “… inverting the composite model to determine an average recipe …”. The limitation of “… inverting the composite model to determine an average recipe …” (U.S. Patent Publication No. 2025/0199521 A1: pgs. 2-3, par. [0028]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A, prong two, the judicial exception is not integrated into a practical application. In particular, the claim recites “… the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors are based on the average recipe”. The limitation of “… the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors are based on the average recipe” is a recitation of the words “apply it” (or an equivalent). “As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do "‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’". Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965).” (see MPEP 2106.05(f)) Accordingly, the additional element does not individually integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the limitation of “… the causing of the fabrication of the first semiconductors and the causing of the fabrication of the second semiconductors are based on the average recipe”, as discussed above, represents an equivalent recitation of the phrase “apply it”, wherein the courts have identified limitations that “(m)erely recit(e) the words ‘apply it’ (or an equivalent)” with the judicial exception cannot provide an inventive concept …”. (see MPEP 2106.04(d)(I)). Considering the additional element individually and the claim as a whole, the additional element does not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 6: At step 2A, prong one, the claim recites “… weighting at least one parameter of the first input parameters or the second input parameters, wherein the composite input parameters are generated based on the weighting of the at least one parameter”. The limitation of “… weighting at least one parameter of the first input parameters or the second input parameters, wherein the composite input parameters are generated based on the weighting of the at least one parameter” (U.S. Patent Publication No. 2025/0199521 A1: pg. 3, par. [0030]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Claim 7: At step 2A, prong one, the claim recites “… the generating of the composite input parameters comprises matching the first input parameters and the second input parameters”. The limitation of “… the generating of the composite input parameters comprises matching the first input parameters and the second input parameters” (U.S. Patent Publication No. 2025/0199521 A1: pg. 2, par. [0027]) is a process performed by use of a mathematical calculation(s). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitations per use of mathematical calculations, then it falls within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Claim 8: Claim 8 represents an equivalent non-transitory machine-readable storage medium claim to claim 1 and is rejected under the same rationale as claim 1. Further, at step 2A, prong two, the judicial is not integrated into a practical application. In particular, the claim recites “… the computer-readable storage medium storing instructions that when executed by one or more processing devices …”. The limitation of “… the computer-readable storage medium storing instructions that when executed by one or more processing devices …” is recited at a high level of generality and recited so generically that it represents no more than mere instructions to apply the judicial exception on a computer component (see MPEP 2106.05(f)). Accordingly, the additional element does not individually integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the element of “… the computer-readable storage medium storing instructions that when executed by one or more processing devices …”, amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. See MPEP 2106.05(d)(II), “Courts have held computer ‐ implemented processes not to be significantly more than an abstract idea (and thus ineligible) where the claim as a whole amounts to nothing more than generic computer functions merely used to implement an abstract idea, such as an idea that could be done by a human analog (i.e., by hand or by merely thinking).” Considering the additional element individually and the claim as a whole, the additional element does not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 9: Claim 9 represents an equivalent non-transitory machine-readable storage medium claim to claim 2 and is rejected under the same rationale as claim 2. Claim 10: Claim 10 represents an equivalent non-transitory machine-readable storage medium claim to claim 3 and is rejected under the same rationale as claim 3. Claim 11: Claim 11 represents an equivalent non-transitory machine-readable storage medium claim to claim 4 and is rejected under the same rationale as claim 4. Claim 12: Claim 12 represents an equivalent non-transitory machine-readable storage medium claim to claim 5 and is rejected under the same rationale as claim 5. Claim 13: Claim 13 represents an equivalent non-transitory machine-readable storage medium claim to claim 6 and is rejected under the same rationale as claim 6. Claim 14: Claim 14 represents an equivalent non-transitory machine-readable storage medium claim to claim 7 and is rejected under the same rationale as claim 7. Claim 15: Claim 15 represents an equivalent system claim to claim 1 and is rejected under the same rationale as claim 1. Further, at step 2A, prong two, the judicial is not integrated into a practical application. In particular, the claim recites “… a memory …” and ”… one or more processors coupled to the memory …”. The limitations of “… a memory …” and :”… one or more processors coupled to the memory …” are recited at a high level of generality and recited so generically that they represent no more than mere instructions to apply the judicial exception on a computer component (see MPEP 2106.05(f)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limitations on practicing the abstract idea. Thus, the claim is directed to an abstract idea. At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As previously discussed with respect to the integration of the abstract idea into a practical application, the addition of the elements of “… a memory …” and :”… one or more processors coupled to the memory …”, amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. See MPEP 2106.05(d)(II), “Courts have held computer ‐ implemented processes not to be significantly more than an abstract idea (and thus ineligible) where the claim as a whole amounts to nothing more than generic computer functions merely used to implement an abstract idea, such as an idea that could be done by a human analog (i.e., by hand or by merely thinking).” Considering the additional elements individually and in combination and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible. Claim 16: Claim 16 represents an equivalent system claim to claim 2 and is rejected under the same rationale as claim 2. Claim 17: Claim 17 represents an equivalent system claim to claim 3 and is rejected under the same rationale as claim 3. Claim 18: Claim 18 represents an equivalent system claim to claim 4 and is rejected under the same rationale as claim 4. Claim 19: Claim 19 represents an equivalent system claim to claim 5 and is rejected under the same rationale as claim 5. Claim 20: Claim 20 represents an equivalent system claim to claim 6 and is rejected under the same rationale as claim 6. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are cited to further show the state of the art with respect to production systems and semiconductor manufacturing systems. U.S. Patent Publication No. 2003/0003607 A1 discloses a plasma processing control system and method that suppresses influences caused by disturbances. U.S. Patent Publication No. 2005/0032459 A1 discloses methods for qualifying a chemical mechanical planarization tool using metrology data measured from a single wafer. U.S. Patent Publication No. 2006/0217910 A1 discloses a method and system for yield similarity of semiconductor devices. U.S. Patent No. 6,607,926 B1 discloses a method and apparatus for controlling manufacturing processes using a hierarchical system. U.S. Patent No. 11,860,591 B2 discloses process recipe creation and matching using feature models. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER L NORTON whose telephone number is (571)272-3694. The examiner can normally be reached Monday - Friday 9:00 am - 5:30 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Robert Fennema can be reached at 571-272-2748. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JENNIFER L NORTON/Primary Examiner, Art Unit 2117 Application/Control Number: 19/071,301 Page 2 Art Unit: 2117 Application/Control Number: 19/071,301 Page 3 Art Unit: 2117 Application/Control Number: 19/071,301 Page 4 Art Unit: 2117 Application/Control Number: 19/071,301 Page 5 Art Unit: 2117 Application/Control Number: 19/071,301 Page 6 Art Unit: 2117 Application/Control Number: 19/071,301 Page 7 Art Unit: 2117 Application/Control Number: 19/071,301 Page 8 Art Unit: 2117 Application/Control Number: 19/071,301 Page 9 Art Unit: 2117 Application/Control Number: 19/071,301 Page 10 Art Unit: 2117
