Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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1. Claims 1-5, 11-14, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,254,316. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would be anticipated by those of ‘316.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-5, 11-14, and 18 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Afshar et al (US 2019/0369994, cited in the IDS dated March 5th, 2025, herein Afshar) in view of Fowers et al (US 2018/0341483, cited in the IDS dated March 5th, 2025, herein Fowers).
Regarding claim 1, Afshar teaches a programmable logic device comprising:
a plurality of vector registers configurable to store a plurality of vectors (Fig 1, [0019], vector register file 120);
switch circuitry communicatively coupled to the plurality of vector registers, wherein the switch circuitry is configurable to route a portion of the plurality of vectors (Fig 1, [0019], crossbar switch 116); and
a plurality of vector processing units implemented on one or more digital signal processing (DSP) blocks of the programmable logic device ([0039], DSP implementation), wherein the plurality of vector processing units is communicatively coupled to the switch circuitry (Fig 1, [0019], PEs 106); and configurable to receive the portion of the plurality of vectors ([0019-0023], access VRF); and
control circuitry configurable to:
receive an instruction to perform an operation involving the portion of the plurality of vector inputs ([0019-0021], execute instructions in PEs); and
cause the portion of the plurality of vectors to be assigned to a first vector processing unit of the plurality of vector processing units ([0019], decoder & scheduler to assign instructions to PEs using values from VRF).
Afshar fails to explicitly teach the control circuitry causing the portion of the plurality of vectors to be routed from the vector registers to the vector processing unit.
Fowers teaches a programmable logic device comprising a plurality of vector processing units configurable to perform one or more operations involving a portion of a plurality of vector inputs, wherein control circuitry is configurable to cause a portion of a plurality of vectors to be routed from vector registers to the vector processing unit ([0031-0037], operations on input tensor vectors including multiplication, addition, etc, [0045], [0054-0060], routing of tensors to calculators according to decoder control).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Afshar and Fowers to utilize the exemplary vector processing system for routing of inputs for arithmetic operations. While Afshar does not explicitly state that the decoder and scheduling may also perform input routing, both Afshar and Fowers disclose techniques for operating on vectors and using an instruction decoder for controlling instruction execution. Therefore, utilizing the vector processing system for such operations would merely entail a simple substitution of known prior art elements to achieve predictable results.
Regarding claim 2, the combination of Afshar and Fowers teaches the programmable logic device of claim 1, comprising one or more memory banks that store the plurality of vectors (Afshar [0022], memory banks).
Regarding claim 3, the combination of Afshar and Fowers teaches the programmable logic device of claim 1, comprising the control circuitry configurable to cause an output from the first vector processing unit to be written to the plurality of vector registers (Afshar [0023], write results to VRF).
Regarding claim 4, the combination of Afshar and Fowers teaches the programmable logic device of claim 1, wherein the operation comprises a vector-vector multiplication operation (Fowers [0031], vector-vector multiply).
Regarding claim 5, the combination of Afshar and Fowers teaches the programmable logic device of claim 1, wherein the operation comprises a vector-addition operation (Fowers [0031], vector addition).
Claim 11 refers to a system embodiment of the device embodiment of claim 2. The above rejection for claim 2 is thus applicable to claim 11.
Regarding claim 12, the combination of Afshar and Fowers teaches the vector processing system of claim 11, wherein the plurality of vector processing units comprise a second vector processing unit, and wherein the first vector processing unit comprises first interconnect circuitry and the second vector processing unit comprises second interconnect circuitry (Afshar Fig 1, [0019], crossbar switch & per-PE channels to read & write data).
Regarding claim 13, the combination of Afshar and Fowers teaches the vector processing system of claim 12, wherein the first vector processing unit and the second vector processing unit are communicatively coupled to one another via the first interconnect circuitry and the second interconnect circuitry (Afshar Fig 1, [0019], channels & switch).
Regarding claim 14, the combination of Afshar and Fowers teaches the vector processing system of claim 12, wherein the second vector processing unit is configurable to receive an output from the first vector processing unit and perform the operation involving the output and a value from the portion of the plurality of vectors (Afshar [0019], exchanging vectors between PEs for processing).
Claim 18 refers to a circuit embodiment of the device embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 18.
3. Claim(s) 6-10, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Afshar and Fowers as applied to claims 1, 11, and 18 above, and further in view of Laurenti et al (US 6,658,578).
Regarding claim 6, the combination of Afshar and Fowers teaches the programmable logic device of claim 1. Afshar and Fowers fail to teach wherein the operation is a conditional operation.
Laurenti teaches a programmable logic device configured to perform a vector processing operation, wherein the operation is a conditional operation (Fig 3, Table 61, 111:5-113:40, conditional instructions and various conditions to be used).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Afshar and Fowers with those of Laurenti to utilize conditional operations. While neither Afshar nor Fowers discloses the use of condition codes or other conditional operations and instructions, one of ordinary skill in the art would understand that the use of conditioned operations is a routine and conventional aspect of the microprocessor art. Therefore, implementing standard condition values and registers, as disclosed by Laurenti, would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 7, the combination of Afshar, Fowers, and Laurenti teaches the programmable logic device of claim 6, wherein the conditional operation comprises a greater than, less than, or equal to a condition (Laurenti Table 61, greater, less, and equal condition encoding).
Regarding claim 8, the combination of Afshar, Fowers, and Laurenti teaches the programmable logic device of claim 7, comprising a plurality of flag registers, wherein the programmable logic device is configurable to determine whether the condition of the conditional operation is present and, in response to determining the condition is present, generate a flag in the plurality of flag registers (Laurenti Fig 3, 8:58-65, flag, status, and vector registers, Table 61, condition field, 111:5-112:67, 118:4-8 & 56:24-27, Table 22, conditional instruction types).
Regarding claim 9, the combination of Afshar, Fowers, and Laurenti teaches the programmable logic device of claim 8, wherein the programmable logic device is configurable to perform the operation, determine whether a flag corresponding to the operation is present in the plurality of flag registers, and refrain from writing a result of the operation to be written to the plurality of vector registers when the flag corresponding to the operation is present (Laurenti Fig 3, 8:58-65, flag, status, and vector registers, Table 61, condition field, 111:5-112:67, 118:4-8 & 56:24-27, Table 22, conditional instruction types).
Regarding claim 10, the combination of Afshar, Fowers, and Laurenti teaches the programmable logic device of claim 9, wherein the programmable logic device is configurable to determine whether the flag is present prior to performing the operation (Laurenti Table 61, condition field, 111:5-112:67, 118:4-8 & 56:24-27, Table 22, conditional instruction types).
Claims 15-17 refer to a system embodiment of the device embodiment of claims 6, 8, and 9. Therefore, the above rejections for claims 6, 8, and 9 are applicable to claims 15-17, respectively.
Claims 19 and 20 refer to a circuit embodiment of the device embodiment of claims 6 and 8. Therefore, the above rejections for claims 6 and 8 are applicable to claims 19 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hung (US 2013/0185544) discloses a vector processor that utilizes a flag register to control execution of SIMD lanes.
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/MICHAEL J METZGER/Primary Examiner, Art Unit 2183
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