DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claim 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In line 1 of claim 10, “the reception circuit” lacks antecedent basis. It is unclear from the claim language if “a low noise amplifier” in line 3 is the same or different from “a low noise amplifier” in line 3 of claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Peiris et al. (US 8340602 B1), hereinafter, Peiris.
Regarding claim 1:
Peiris discloses a radio frequency (RF) transceiver circuit (Fig. 3), comprising:
a transmission circuit, arranged to generate a transmission signal (Fig. 3, transmitter portion circuitry in the transmit path 120 comprises claimed transmission circuit), wherein the transmission signal is transmitted to an antenna (Fig. 3, antenna 148)(Column 6, lines 26-44; column 7, lines 38-40);
a reception circuit (Fig. 3, receiver portion circuity in receive path 122 comprises claimed reception circuit), arranged to receive a reception signal through the antenna(Fig. 3, antenna 148)(Column 6, lines 26-44); and
a pre-distortion processing circuit (Fig.3), comprising:
a feedback signal is generated according to a coupling signal of the transmission signal (Fig. 3, Column 6, lines 26-44; looped back signal is claimed feedback signal);
a mixer (Fig. 3, 154), arranged to perform a down-conversion operation upon the signal via an oscillation signal (Column 7, lines 48-52) to generate a mixed signal;
a second filter arranged to perform filtering to generate a filtered signal (Column 10, lines 44-48);
an analog-to-digital converter (Fig. 3, ADC 162), arranged to perform an analog-to-digital conversion operation upon the filtered signal (Column 10, lines 44-48)to generate a digital signal (Column 7, lines 47-62); and
a digital processing circuit, arranged to calculate distortion information of the transmission signal according to the digital signal, in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation (Column 9, line 55-column 11, line 17; all the circuitry between ADC 162 and predistorter 102 is claimed digital circuitry; output of PTC 182 is provided to predistorter 102 in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation).
Thus, Peiris discloses all the limitations above, but fails to explicitly disclose a first filter, arranged to filter the feedback signal to filter out harmonic components of the feedback signal in order to generate a filtered signal;
down-conversion operation on the filtered signal and;
a second filter, arranged to perform a low-pass filtering operation upon the mixed signal or an amplified signal to generate a low-pass filtered signal, wherein the amplified signal is generated by an amplifier performing an amplification operation upon the mixed signal.
However, Bai discloses a radio frequency transceiver with a predistortion processing circuit (Fig. 8) comprising:
a first filter (Fig. 8, filter 94), arranged to filter a feedback signal to filter out harmonic components of the feedback signal in order to generate a filtered signal (Column 10, lines 40-45; filtering out-of band distortion is claimed filter out harmonic components);
down-conversion on a filtered signal (Column 10, lines 40-54, down-coverter 98 performs down-conversion on a filtered signal) and
a second filter (Fig. 8; filter 100), arranged to perform a low-pass filtering operation upon the mixed signal or an amplified signal to generate a low-pass filtered signal, wherein the amplified signal is generated by an amplifier performing an amplification operation upon the mixed signal (Fig. 8, filter 100, column 10, lines 52-55; amplified signal limitation is optional and thus not shown; downcoverted signal is claimed mixed signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ predistortion processing circuitry to incorporate the first filter, the downconversion operation of the filtered signal and the second filter as disclosed by Bai, thereby arriving at claimed invention. It would have been obvious because incorporating the filters reduces noise in the predistortion processing circuitry.
3. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Peiris and Bai as applied to claim 1 above, and further in view of Vassiliou et al. (US 20060178165 A1), hereinafter, Vassiliou.
Regarding claim 2:
Peiris and Bai disclose all the limitations of claim 1 above, but fail to explicitly disclose the RF transceiver circuit, wherein the pre-distortion processing circuit comprises: a single-to-differential converter, arranged to convert the feedback signal into a differential signal; wherein the first filter is arranged to filter the differential signal to generate the filtered signal.
Vassiliou discloses the RF transceiver circuit, wherein the pre-distortion processing circuit further comprises: a single-to-differential converter, arranged to convert the feedback signal into a differential signal; wherein the first filter is arranged to filter the differential signal to generate the filtered signal (Paragraphs [0062], [0036]-[0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ receiver as modified by Bai to incorporate conversion to differential signal and processing as disclosed by Vassiliou, thereby arriving at claimed invention. It would have been obvious because incorporating differential signals minimizes crosstalk and externally induced noise (Paragraph [0037]).
Regarding claim 3:
Peiris and Bai disclose all the limitations of claim 1 above.
Peiris further discloses
the mixer (Fig. 3, 154);
wherein when the RF transceiver circuit operates in a reception mode, the reception signal is sequentially processed by the receiver including the mixer (Column 6, lines 37-41; column 7, lines 43-51);
wherein when the RF transceiver circuit operates in a test mode (Column 6, lines 27-37, training is claimed test mode), the pre-distortion processing circuit utilizes the mixer to calculate the distortion information of the transmission signal according to the feedback signal, in order to generate and transmit the compensation signal to the transmission circuit for performing the pre-distortion compensation operation (Column 9, line 55-column 11, line 17).
Thus, Peiris and Bai disclose all limitations of claim 3 above, but fail to explicitly disclose a low-noise amplifier; a transformer; and sequential processing including the low-noise amplifier and the transformer.
However, Vassiliou discloses
a low-noise amplifier (Fig. 3, LNA 114a; paragraph [0062]);
a transformer ( Fig. 3, transformer in RX path; paragraph [0062]); and
sequential processing of received signal including the low-noise amplifier and the transformer (See Fig. 3, paragraphs [0039], [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ receiver as modified by Bai to incorporate low noise amplifier and transformer as disclosed by Vassiliou, thereby arriving at claimed invention. It would have been obvious because incorporating receiver components allows for coupling and amplification for more effective processing by a receiver.
4. Claims 8 are rejected under 35 U.S.C. 103 as being unpatentable over Peiris in view of Chee et al. (US 20160105299 A1), hereinafter Chee, and Bai.
Regarding claim 8:
Peiris discloses a circuit set (Fig. 3), comprising:
a power amplifier (Fig. 3, PA 146) is arranged to amplify a transmission signal for transmitting through an antenna (Column 7, lines 28-47).
a coupler, arranged to generate a coupling signal according to the transmission signal (Column 7, lines 28-47; switch 150 is claimed coupler).;
a matching circuit, arranged to generate a feedback signal according to the coupling signal (Column 7, lines 28-47; ATTN 152 is claimed matching circuit); and
a pre-distortion processing circuit (Fig.3), comprising:
a feedback signal is generated according to a coupling signal of the transmission signal (Fig. 3, Column 6, lines 26-44; looped back signal is claimed feedback signal);
a mixer (Fig. 3, 154), arranged to perform a down-conversion operation upon the signal via an oscillation signal (Column 7, lines 48-52) to generate a mixed signal;
a second filter arranged to perform filtering to generate a filtered signal (Column 10, lines 44-48);
an analog-to-digital converter (Fig. 3, ADC 162), arranged to perform an analog-to-digital conversion operation upon the filtered signal (Column 10, lines 44-48)to generate a digital signal (Column 7, lines 47-62); and
a digital processing circuit, arranged to calculate distortion information of the transmission signal according to the digital signal, in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation (Column 9, line 55-column 11, line 17; all the circuitry between ADC 162 and predistorter 102 is claimed digital circuitry; output of PTC 182 is provided to predistorter 102 in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation).
Thus, Peiris discloses all the limitations above, but fails to explicitly disclose
an external front-end module, comprising a power amplifier and a low-noise amplifier, wherein the power amplifier is arranged to amplify a transmission signal for transmitting through an antenna; and the low-noise amplifier is arranged to receive a reception signal through the antenna and a first filter, arranged to filter the feedback signal to filter out harmonic components of the feedback signal in order to generate a filtered signal; down-conversion operation on the filtered signal and; a second filter, arranged to perform a low-pass filtering operation upon the mixed signal or an amplified signal to generate a low-pass filtered signal, wherein the amplified signal is generated by an amplifier performing an amplification operation upon the mixed signal.
However, Chee discloses an external front-end module (Fig. 5, 530), comprising a power amplifier (Fig. 5, PA 534) and a low-noise amplifier (Fig. 5, LNA 536), wherein the power amplifier is arranged to amplify a transmission signal for transmitting through an antenna (Fig. 5, antenna 520); and the low-noise amplifier is arranged to receive a reception signal through the antenna (Paragraphs [0049], [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ circuitry to incorporate the power amplifier in an external front end module comprising the low noise amplifier as disclosed by Chee. It would have been obvious because the front end module provides a good interface between an antenna and a transceiver (Paragraph [0048]).
Further, Bai discloses a radio frequency transceiver with a predistortion processing circuit (Fig. 8) comprising:
a first filter (Fig. 8, filter 94), arranged to filter a feedback signal to filter out harmonic components of the feedback signal in order to generate a filtered signal (Column 10, lines 40-45; filtering out-of band distortion is claimed filter out harmonic components);
down-conversion on a filtered signal (Column 10, lines 40-54, down-coverter 98 performs down-conversion on a filtered signal) and
a second filter (Fig. 8; filter 100), arranged to perform a low-pass filtering operation upon the mixed signal or an amplified signal to generate a low-pass filtered signal, wherein the amplified signal is generated by an amplifier performing an amplification operation upon the mixed signal (Fig. 8, filter 100, column 10, lines 52-55; amplified signal limitation is optional and thus not shown; downcoverted signal is claimed mixed signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify Peiris’ circuitry as modified by Chee so that Peris’ predistortion processing circuitry incorporates the first filter, the downconversion operation of the filtered signal and the second filter as disclosed by Bai, thereby arriving at claimed invention. It would have been obvious because incorporating the filters reduces noise in the predistortion processing circuitry.
5. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Peiris, Chee and Bai as applied to claim 8 above, and further in view of Vassiliou.
Regarding claim 9:
Peiris, Chee and Bai disclose all the limitations of claim 1 above, but fail to explicitly disclose the circuit, wherein the pre-distortion processing circuit further comprises: a single-to-differential converter, arranged to convert the feedback signal into a differential signal; wherein the first filter is arranged to filter the differential signal to generate the filtered signal.
Vassiliou discloses the RF transceiver circuit, wherein the pre-distortion processing circuit further comprises: a single-to-differential converter, arranged to convert the feedback signal into a differential signal; wherein the first filter is arranged to filter the differential signal to generate the filtered signal (Paragraphs [0062], [0036]-[0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ receiver as modified by Chee and Bai to incorporate conversion to differential signal and processing as disclosed by Vassiliou, thereby arriving at claimed invention. It would have been obvious because incorporating differential signals minimizes crosstalk and externally induced noise (Paragraph [0037]).
Regarding claim 10:
Peiris, Chee and Bai disclose all the limitations of claim 1 above.
Peiris further discloses
the mixer (Fig. 3, 154);
wherein when the RF transceiver circuit operates in a reception mode, the reception signal is sequentially processed by the receiver including the mixer (Column 6, lines 37-41; column 7, lines 43-51);
wherein when the RF transceiver circuit operates in a test mode (Column 6, lines 27-37, training is claimed test mode), the pre-distortion processing circuit utilizes the mixer to calculate the distortion information of the transmission signal according to the feedback signal, in order to generate and transmit the compensation signal to the transmission circuit for performing the pre-distortion compensation operation (Column 9, line 55-column 11, line 17).
Chee discloses the low noise amplifier (Fig. 5, LNA 536), Paragraphs [0049], [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ circuitry to incorporate the power amplifier in an external front end module comprising the low noise amplifier as disclosed by Chee. It would have been obvious because the front end module provides a good interface between an antenna and a transceiver (Paragraph [0048]).
Thus, Peiris, Chee and Bai disclose all limitations of claim 10 above, but fail to explicitly disclose; a transformer; and sequential processing including the low-noise amplifier and the transformer.
However, Vassiliou discloses a low-noise amplifier (Fig. 3, LNA 114a; paragraph [0062]);
a transformer ( Fig. 3, transformer in RX path; paragraph [0062]); and
sequential processing of received signal including the low-noise amplifier and the transformer (See Fig. 3, paragraphs [0039], [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Peiris’ receiver as modified by Chee and Bai to incorporate the transformer as disclosed by Vassiliou, thereby arriving at claimed invention. It would have been obvious because incorporating receiver components allows for coupling and amplification for more effective processing by a receiver.
Allowable Subject Matter
5. Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINEETA S PANWALKAR whose telephone number is (571)272-8561. The examiner can normally be reached M-F 9:00am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David C. Payne can be reached at 571-272-3024. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VINEETA S PANWALKAR/Primary Examiner, Art Unit 2635
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