DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/11/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Reference Uzoh et al. (US Publication No. 2024/0186268) is introduced below to teach the amended limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hurwitz et al. (US Publication No. 2015/0294896) in view of Uzoh et al. (US Publication No. 2024/0186268).
Regarding claim 11, Hurwitz discloses a subsystem tile for electronics, the subsystem tile comprising (Figure 9):
a rigid tile (208) portion comprising at least one cavity (126) configured to receive an electronic component (202) with interconnect wiring (204) (Paragraph 108 describes reinforced polymer with inorganic fillers, therefore rigid)
a polymer-based laminate frame (206) disposed around rigid tile portion (208)
at least one vertical interconnect (210) disposed within the polymer-based laminate frame (206)
Hurwitz does not disclose a gap-fill polymer material filling the at least one cavity of the rigid tile portion. However, Uzoh discloses a polymer gap-fill material (70) which fills a cavity of a rigid tile portion (20/30) within a polymer-based laminate frame (76) (paragraph 81). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify Hurwitz to form a cavity for an electronic component as taught by Uzoh, since it can prevent or mitigate carrier warpage by providing a more uniform stress distribution at the interface or surface of the carrier (paragraphs 50-51).
Regarding claim 12, Hurwitz discloses the rigid tile portion being formed of an inorganic material (paragraph 109 shows inorganic fillers such as ceramic particles).
Regarding claim 13, Hurwitz discloses the at least one cavity being configured to receive at least one of an analog chip, a mixed signal chip, and a digital chip (paragraph 28).
Regarding claim 15, Hurwitz discloses the at least one cavity being configured to receive at least one of an inductor, a capacitor, and a power management integrated circuit (paragraph 101).
Claims 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Publication No. 2020/0105687) in view of Hurwitz et al. (US Publication No. 2015/0294896), and further in view of Uzoh et al. (US Publication No. 2024/0186268).
Regarding claim 11, Wang discloses a subsystem tile for electronics, the subsystem tile comprising:
a rigid tile (604) portion comprising at least one cavity configured to receive an electronic component (300) with interconnect wiring (312a)
a polymer frame (404) disposed around rigid tile portion (604)
at least one vertical interconnect (200) disposed within the polymer frame (404)
Wang does not disclose the frame to be a polymer-based laminate. However, Hurwitz discloses a frame (206) made of polymer-based laminate (paragraph 109). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the frame of Wang to be formed of a polymer-based laminate, as taught by Hurwitz, since it can improve manufacturing to allow for a thinner, better heat dissipation, and a better planarity device (paragraph 5).
Wang does not disclose a gap-fill polymer material filling the at least one cavity of the rigid tile portion. However, Uzoh discloses a polymer gap-fill material (70) which fills a cavity of a rigid tile portion (20/30) within a polymer-based laminate frame (76) (paragraph 81). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify the device of Wang to form a cavity for an electronic component as taught by Uzoh, since it can prevent or mitigate carrier warpage by providing a more uniform stress distribution at the interface or surface of the carrier (paragraphs 50-51).
Regarding claim 12, Wang discloses the rigid tile portion being formed of an inorganic material (paragraph 39).
Regarding claim 13, Wang discloses the at least one cavity being configured to receive at least one of an analog chip, a mixed signal chip, and a digital chip (paragraph 50).
Regarding claim 15, Wang discloses the at least one cavity being configured to receive at least one of an inductor, a capacitor, and a power management integrated circuit (paragraph 31).
Claims 1-10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Publication No. 2022/0157677) in view of Wang et al. (US Publication No. 2020/0105687), and further in view of Hurwitz et al. (US Publication No. 2015/0294896), and further in view of Uzoh et al. (US Publication No. 2024/0186268).
Regarding claim 1, Lin discloses a heterogeneous multifunctional package architecture, comprising:
a first substrate (170) configured to support interconnect wiring (160), the first substrate (170) being multilayered, and the first substrate comprising a substrate chipset (150 of four chipsets)
a plurality of subsystem tiles (IS1-4) disposed within the first substrate (170) and comprising an active tile chipset (150 of four chipsets)
a planar interconnect (180) scheme between the active tile chipset (150) and the substrate chipset (150)
the first substrate (170) being double-sided such that an upper surface of the first substrate (150) and a lower surface of the first substrate are both configured to electrically connect to electrical components (Figure 13)
the upper surface of the first substrate (170) being opposite from the lower surface of the first substrate (Figure 13)
While Lin discloses the use of passive components formed on the redistribution structure (180) (paragraph 35), Lin does not specifically disclose passive electronic components in the first substrate as a substrate chipset. However, Wang discloses a chip (310) which can have active and passive components (paragraph 31). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Lin to include both active and passive chips, as taught by Wang, since it can increase versatility if a package by including multiple functioning chips for a variety of applications (paragraphs 50-51).
Wang does not disclose the first substrate to be an organic laminate substrate and the subsystem tiles to be inorganic. However, Hurwitz discloses a substrate (206) made of organic polymer-based laminate (paragraph 109) and the subsystem tiles (208) to be inorganic (Paragraph 108 describes reinforced polymer with inorganic fillers, therefore rigid). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the substrate of Wang to be formed of a polymer-based laminate, as taught by Hurwitz, since it can improve manufacturing to allow for a thinner, better heat dissipation, and a better planarity device (paragraph 5), and the inorganic subsystem tiles to be inorganic to improve stiffness, and therefore the integrity of the device (paragraph 88).
Wang does not disclose a gap-fill polymer material between chip walls of the active tile chipset of the plurality of inorganic subsystem tiles, and between the first substrate and the plurality of inorganic subsystem tiles. However, Uzoh discloses a polymer gap-fill material (70) which fills a cavity of inorganic subsystem tiles (20/30) between chip (12) walls and between the first substrate (90) (Figure 10F) and the plurality of inorganic subsystem tiles (20/30) (Figure 7H; paragraph 81). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify Wang to form a cavity for an electronic component as taught by Uzoh, since it can prevent or mitigate carrier warpage by providing a more uniform stress distribution at the interface or surface of the carrier (paragraphs 50-51).
Regarding claim 2, Wang discloses the plurality of subsystem tiles supporting at least one beamforming chip (paragraph 50).
Regarding claim 3, Wang discloses the plurality of subsystem tiles supporting at least one frequency conversion chip (paragraph 50).
Regarding claim 4, Wang discloses the first substrate comprising a beamforming communication device integrated therewith (paragraph 50).
Regarding claim 5, Wang discloses the plurality of subsystem tiles supporting at least one inductor, at least one capacitor (paragraph 31), and Lin discloses at least one power management integrated circuit (IC) (paragraph 30).
Regarding claim 6, Lin discloses a second substrate (300) electrically connected to the first substrate by at least one metal interconnect array (190).
Regarding claim 7, Lin discloses a digital chip (300) electrically connected to the first substrate (170), such that the heterogeneous multifunctional package architecture forms a computing device.
Regarding claim 8, Lin discloses a vertical interconnect (170) configured to connect to a second substrate (300) configured to be an interposer circuit board (paragraph 40).
Regarding claim 9, Lin discloses the second substrate (300), and the second substrate being a digital chip interposer (paragraph 40).
Regarding claim 10, Lin discloses the second substrate (300), and the second substrate being a power device interposer (paragraph 40).
Regarding claim 20, Lin discloses a heterogeneous multifunctional package architecture, comprising:
a first substrate (170) configured to support interconnect wiring (160), the first substrate (170) being multilayered, and the first substrate comprising a substrate chipset (150 of four chipsets)
a plurality of subsystem tiles (IS1-4) disposed within the first substrate (170) and comprising an active tile chipset (150 of four chipsets)
a planar interconnect (180) scheme between the active tile chipset (150) and the substrate chipset (150)
the first substrate (170) being double-sided such that an upper surface of the first substrate (150) and a lower surface of the first substrate are both configured to electrically connect to electrical components (Figure 13)
the upper surface of the first substrate (170) being opposite from the lower surface of the first substrate (Figure 13)
the plurality of subsystem tiles (IS1-4) supporting at least one of the following: a beamforming chip; a frequency conversion chip; an inductor; a capacitor; and a power management integrated circuit (paragraph 35)
the heterogeneous multifunctional package architecture (paragraph 27) further comprising a second substrate (300) electrically connected to the first substrate (170) by at least one metal interconnect array (190)
and the second substrate (300) being a digital chip interposer (PCB) or a power device interposer (paragraph 40)
While Lin discloses the use of passive components formed on the redistribution structure (180) (paragraph 35), Lin does not specifically disclose passive electronic components in the first substrate as a substrate chipset. However, Wang discloses a chip (310) which can have active and passive components (paragraph 31). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Lin to include both active and passive chips, as taught by Wang, since it can increase versatility if a package by including multiple functioning chips for a variety of applications (paragraphs 50-51).
Lin does not disclose the first substrate to be an organic laminate substrate and the subsystem tiles to be inorganic. However, Hurwitz discloses a substrate (206) made of organic polymer-based laminate (paragraph 109) and the subsystem tiles (208) to be inorganic (Paragraph 108 describes reinforced polymer with inorganic fillers, therefore rigid). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the substrate of Lin to be formed of a polymer-based laminate, as taught by Hurwitz, since it can improve manufacturing to allow for a thinner, better heat dissipation, and a better planarity device (paragraph 5), and the inorganic subsystem tiles to be inorganic to improve stiffness, and therefore the integrity of the device (paragraph 88).
Lin does not disclose a gap-fill polymer material filling the at least one cavity of the rigid tile portion. However, Uzoh discloses a polymer gap-fill material (70) which fills a cavity of a rigid tile portion (20/30) within a polymer-based laminate frame (76) (paragraph 81). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to modify Lin to form a cavity for an electronic component as taught by Uzoh, since it can prevent or mitigate carrier warpage by providing a more uniform stress distribution at the interface or surface of the carrier (paragraphs 50-51).
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Publication No. 2020/0105687) in view of Hurwitz et al. (US Publication No. 2015/0294896), in view of Uzoh et al. (US Publication No. 2024/0186268), and further in view of Lin et al. (US Publication No. 2022/0157677).
Regarding claim 14, Wang/Hurwitz/Uzoh discloses the limitations as discussed in the rejection of claim 11 above. Wang also discloses beam steering antenna in package (paragraph 50). Wang does not disclose an antenna-in-package interconnected with the subsystem tile according to the subsystem tile comprising an analog chip disposed in a first cavity of the at least one cavity, a mixed signal chip disposed in a second cavity of the at least one cavity, and a digital chip disposed in a third cavity of the at least one cavity. However, Lin discloses an analog chip disposed in a first cavity of the at least one cavity, a mixed signal chip disposed in a second cavity of the at least one cavity, and a digital chip disposed in a third cavity of the at least one cavity (paragraph 30). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Wang/Hurwitz to include the variety of chips in the cavities, since it can increase versatility if a package by including multiple functioning chips for a variety of applications (paragraph 30).
Regarding claim 16, Wang/Hurwitz discloses the limitations as discussed in the rejection of claim 11 above. Wang/Hurwitz also discloses a computing device, comprising: a digital chip (300) interconnected with the subsystem tile. Wang/Hurwitz does not disclose an inductor disposed in a first cavity of the at least one cavity, a capacitor disposed in a second cavity of the at least one cavity, and a power management integrated circuit disposed in a third cavity of the at least one cavity. However, Lin discloses an inductor disposed in a first cavity of the at least one cavity, a capacitor disposed in a second cavity of the at least one cavity, and a power management integrated circuit disposed in a third cavity of the at least one cavity (paragraph 30). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Wang to include the variety of chips in the cavities, since it can increase versatility if a package by including multiple functioning chips for a variety of applications (paragraph 30).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Publication No. 2020/0105687) in view of Hurwitz et al. (US Publication No. 2015/0294896), in view of Uzoh et al. (US Publication No. 2024/0186268), and further in view of Fitzsimmons et al. (US Publication No. 2019/0035735).
Regarding claim 17, Wang/Hurwitz/Uzoh discloses the limitations as discussed in the rejection of claim 11 above. Wang/Hurwitz does not disclose a stack of thin ceramic films and metal films disposed in the at least one cavity, the metal films forming extended electrodes on edges of the stack, and the stack being metallized with at least one metal ink. However, Fitzsimmons discloses a stack of thin ceramic films and metal films disposed in the at least one cavity, the metal films forming extended electrodes on edges of the stack, and the stack being metallized with at least one metal ink (paragraph 25). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Wang/Hurwitz to include the stack, as taught by Fitzsimmons, it can increase versatility if a package by including multiple functioning chips for a variety of applications formed through improved adhesion and reliability in applications directed to selective metallization of substrates (paragraph 22).
Regarding claim 18, Wang discloses the stack being fan-out interconnected to a plurality of electrical components (paragraph 97).
Regarding claim 19, Fitzsimmons the metal films being nickel films (paragraph 25). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Wang et al. in view of Hurwitz et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. US Publication No. 2022/0045014) discloses a chip (170) in a cavity filled with polymer (141) within an inorganic frame (140) with conductive traces on the top and bottom of the chip (Figures 2F-2P).
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/N.R.P/ 2/1/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897