DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 11, 12, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being obvious over Song et al. (hereinafter “Song”), US Pub. No. 2016/0055798, in view of Kim et al. (hereinafter “Kim”), US Pub. No. 2024/0355268.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 1, Song teaches a display apparatus (fig. 1, display 100) comprising: a display panel including a pixel circuit (fig. 1, display panel 110, pixel P); a gate emission driver configured to output gate signals to the display panel (fig. 1, scan driving unit 120); a data driver configured to apply a data voltage to the display panel (fig. 1, data driving unit 130); and a block control driver configured to output a block control signal to the display panel (fig. 1, emission driving unit 140, [0064]; mode control unit 145 controls the emission driving unit 140 to sequentially provide the emission control signals to the display panel 110… emission driving unit 140 includes first through (n)th emission driving blocks in parallel).
Song fails to explicitly teach a driving transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node and configured to generate a driving current based on a voltage of the first node; a writing transistor configured to apply the data voltage to the second node in response to a write gate signal; a block control transistor configured to connect the third node and a fourth node in response to the block control signal; an initialization transistor configured to apply an initialization voltage to the third node in response to an initialization gate signal; a compensation transistor configured to connect the fourth node and the first node in response to a compensation gate signal; and a light emitting element configured to emit light based on the driving current.
However, in the same field of endeavor, Kim teaches a pixel circuit including a driving transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node and configured to generate a driving current based on a voltage of the first node (fig. 2, transistor T1); a writing transistor configured to apply the data voltage to the second node in response to a write gate signal (fig. 2, transistor T2); a block control transistor configured to connect the third node and a fourth node in response to the block control signal (fig. 2, transistor T5); an initialization transistor configured to apply an initialization voltage to the third node in response to an initialization gate signal (fig. 2, transistor T4); a compensation transistor configured to connect the fourth node and the first node in response to a compensation gate signal (fig. 2, transistor T3); and a light emitting element configured to emit light based on the driving current (fig. 2, light emitting element EE).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel of Song to include the pixel circuit of Kim. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to provide a device with increased efficiency.
Regarding claim 8, Kim teaches wherein the writing transistor includes a control electrode for receiving the write gate signal, a first electrode for receiving the data voltage and a second electrode connected to the second node (fig. 2, GW), wherein the compensation transistor includes a control electrode for receiving the compensation gate signal, a first electrode connected to the fourth node and a second electrode connected to the first node (fig. 2, GC), wherein the initialization transistor includes a control electrode for receiving the initialization gate signal, a first electrode for receiving the initialization voltage and a second electrode connected to the third node (fig. 2, GR), and wherein the block control transistor includes a control electrode for receiving the block control signal, a first electrode connected to the third node and a second electrode connected to the fourth node (fig. 2, EM).
Regarding claim 11, Kim teaches wherein the driving transistor and the writing transistor are P-type transistors ([0065, 0067]), and wherein the compensation transistor, the initialization transistor and the block control transistor are N-type transistors ([0065, 0067]).
Regarding claim 12, Kim teaches wherein the gate signals are outputted to the pixel circuit through gate lines extend in a first direction (fig. 1, gate driver 300), wherein the data signal is outputted to the pixel circuit through a data line extend in a second direction different from the first direction (fig. 1, data driver 400), and wherein the block control signal is outputted to the pixel circuit through a block control line extend in the second direction (fig. 1, emission driver 500).
Regarding claim 15, it is a display apparatus of claim 1 and is rejected on the same grounds presented above.
Regarding claim 18, it is a pixel circuit of claim 1 and is rejected on the same grounds presented above.
Regarding claim 20, it is an electronic apparatus of claim 1 and is rejected on the same grounds presented above (Kim further teaches a driving controller, see fig. 1, driving controller 200; and a processor, see fig. 13, processor 1010).
Allowable Subject Matter
Claims 2-7, 9, 10, 13, 14, 16, 17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625